Keithley KPCMCIA-12AIAOH, Руководство пользователя

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KPCMCIA-12AIAOH User’s Manual Theory of Operation 3-7
D/A circuit
The KPCMCIA-12AIAOH PC card is equipped with two D/A channels. The 12-bit serial D/A
converter (AD7249 from analog device) supports synchronous update. It is configured to have a
bipolar output range from -5 to +5V. The 12-bit output data format is always in 2’s complement
(right justified) with the upper four bits indicating the output channel number (binary 0000 for
channel 0 and 0001 for channel 1). The D/A data port occupies two bytes (write only) in the I/O
space.
The serial link from the D/A port to the D/A converter contains a 16-bit buffer register and a
16-bit shift register. A data word written into the D/A port is written into the buffer register, loaded
into the shift register, and sent to the input register of the corresponding D/A channel (inside the
D/A converter AD7249).
Inside the D/A converter, each channel also has a 16-bit shift register, a 12-bit input register, and
a 12-bit output register. The data loaded into the output register determines the analog output of
the D/A channel.
The KPCMCIA-12AIAOH PC card has four D/A operation modes (modes 0 to 3). Mode 0 is the
direct update mode. The corresponding D/A channel output register updates immediately after the
data word is written into the D/A port (if byte I/O is used, after the high byte is written). There is
no synchronization between the two channels in this mode.
Modes 1, 2, and 3 are all using synchronized update, in which the two D/A channels are updated
at the same time (synchronously) for certain events. In mode 1, the event is the timer overflow. In
mode 2, it is the external gate control (going from low to high). In mode 3, the event comes from
the pacer clock.
In the synchronous update modes, the data word written to each D/A channel is buffered in its
input register (inside the AD7249) first and then loaded into the output register (and therefore the
D/A output gets updated) when the corresponding event (depending on the mode) is received.
Synchronous update modes can be used to generate waveforms with accurate phase requirements,
such as orthogonal, sinusoidal waveforms (sine and cosine).
Timer counter
In addition to the 24-bit pacer clock, the KPCMCIA-12AIAOH PC card is equipped with an inde-
pendent 16-bit timer/counter. The timer/counter has an internal clock source of 1MHz and an
external clock input (for counting or as an external clock source, shared with the pacer clock
external input).
The timer circuit contains a 16-bit reload register, a 16-bit up-counter, and a 16-bit read-latch reg-
ister. The reload register holds the initial value for the counter. The counter is also loaded with the
same value each time it overflows. The read-latch register latches the current count of the counter
each time it receives a latch command. The integrity of the latched count is guaranteed by the logic
design.
The 16-bit reload register is accessed when writing into the port, while the read-latch register is
accessed when reading the port. The up-counter cannot be accessed directly.
Either the 1MHz internal clock source or the external clock source (or the counter pulse input) is
software selectable. Because of the I/O pin confinement, the timer external clock input is shared
with pacer clock external input (also shared as the digital input bit 2).