Keithley KPCMCIA-12AIAOH, Руководство пользователя

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KPCMCIA-12AIAOH User’s Manual Theory of Operation 3-5
Interrupt and status
The KPCMCIA-12AIAOH PC card has three interrupt sources: the end-of-scan (EOS) interrupt,
the FIFO threshold interrupt, and the timer interrupt. These interrupts are used as follows:
• When the EOS interrupt is enabled, an interrupt is sent to the host at the end of each scan of
the channel list. If only one channel is in the scan list, the EOS interrupt is reduced to an
EOC (end-of-conversion) interrupt.
• The FIFO threshold interrupt, when enabled, is sent to the host when an almost-full flag is set
by the card. The host can then use the string input instruction to move a block of samples
from the FIFO.
• When the timer interrupt is enabled, an interrupt is sent to the host each time the timer over-
flows.
Digital I/O
The KPCMCIA-12AIAOH PC card has one digital input port (base + 3, read only) of four bits
(bits 0 to 3) and one digital output port (base + 3, write only) of four output bits (bits 0 to 3). The
output port is latched, but the input port is not.
Four input lines are connected to the digital input port; each represents one bit in the port. When
reading the digital input port, the current status of the digital input lines are returned to the host.
All four input lines are shared with other functions. Bit 0 is shared as the external trigger and
external paced clock input. Bit 2 is shared as the external clock burst input. Bits 1 and 3 are taken
over as the external gain selection lines if one or more expansion cards are connected and an
expansion bit is set by software. However, the current status of the digital input lines is always
returned when the host reads the digital input port, whether the lines are shared or not.
The four digital output lines are taken over as the external channel selection lines if an expansion
bit is set by software. In this case, the digital output lines are driven by the external channel selec-
tion bits of the current scan list entry. Otherwise, they are connected to the latched bits 0 through
3 of the digital output port.