Keithley 7070, Инструкция по эксплуатации

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SERVICE INFORMATION
4-4
4.5.2 ID Data Circuits
Upon power-up, the card identi Þ cation data information
from each card is read by the mainframe. This ID data
includes such information as card ID, hardware settling
time for the card, and a relay con
Þ guration table, which tells
the mainframe which relays to close for a speci Þ c crosspoint.
This con Þ guration table is necessary because some cards
require the closing of more than one relay to close a speci Þ c
crosspoint.
ID data is contained within an on-card ROM, U47. In order
to read this information, the sequence below is performed
upon power-up. Figure 4-2 shows the general timing of this
sequence.
1. The CARDSEL line is brought low, enabling the ROM
outputs. This line remains low throughout the ID data
transmission sequence.
2. The CLRADDR line is pulsed high to clear the address
counter and set it to zero. At this point, a ROM address
of zero is selected. This pulse occurs only once.
3. The NEXTADDR line is set low. NEXTADDRS going
low increments the counter and enables parallel loading
of the parallel-to-serial converter. NEXTADDR is kept
low long enough for the counter to increment and for
the ROM outputs to stabilize. This sequence functions
because the load input of the parallel-to-serial converter
is level sensitive rather than edge sensitive. The
Þ rst
ROM address is location 1, not 0.
4. The CLK line clocks the parallel-to-serial converter to
shift all eight data bits from the converter to the main-
frame via the IDDATA line.
Address
Counter
U45
ROM
U47
Parallel
to Serial
Converter
U46
Buffer
U44
Relay
Drivers
U30-U41
User
Installed
Relays
Power-On
Safeguard
U42
A0-A11
D0-D7
CLRADDR
To
Mainframe
NEXTADDR NEXTADDR
CARDSEL
IDDATA
CLK
RELAYDATA
STROBE
Rows
A-H
Columns
1-12
Output
Enable
Figure 4-3. Model 7070 Block Diagram