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5-13
5.5.2 ID data circuits
Upon power-up, card identi
Þ
cation information from
each card is read by the mainframe. This ID data in-
cludes such information as card ID, hardware settling
time, and relay con
Þ
guration information.
ID data is contained within an on-card EEPROM
(U105). In order to read this information, the sequence
described below is performed on power-up.
1. The IDDATA line (pin 6 of U105) is set from high to
low while the IDCLK line (pin 5 of U105) is held
high. This action initiates a start command to the
ROM to transmit data serially to the mainframe
(Figure 5-9).
2. The mainframe sends the ROM address location to
be read over the IDDATA line. The ROM then
transmits an acknowledge signal back to the main-
frame, and it then transmits data at that location
back to the mainframe (Figure 5-10).
3. The mainframe then transmits an acknowledge
signal, indicating that it requires more data. The
ROM will then sequentially transmit data after
each acknowledge signal it receives.
4. Once all data is received, the mainframe sends a
stop command, which is a low-to-high transition
of the IDDATA line with the IDCLK line held high
(see Figure 5-9).
5.5.3 Relay control
Card relays are controlled by serial data transmitted
via the relay DATA line. A total of
Þ
ve bytes for each
card are shifted in serial fashion into latches located in
the card relay driver ICs. The serial data is clocked in
by the CLK line. As data over
ß
ows one register, it is fed
out the Q’S line of the register down the chain.
Once all
Þ
ve bytes have shifted into the card, the
STROBE line is set high to latch the relay information
into the Q outputs of the relay drivers, and the appro-
priate relays are energized (assuming the driver out-
puts are enabled, as discussed below). Note that a relay
driver output goes low to energize the corresponding
relay.
Figure 5-9
Start and stop sequences
ID CLK
ID DATA
Start Bit
Stop Bit
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