JYTEK PXIe-2722, Руководство пользователя

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PXIe-2722 Chassis | jytek.com | 42
Reference Clock Status Display in JYDM
JYDM can display the 10MHz reference clock(PXI_CLK10) source which come from
onboard (backplane’s local oscillator) or external (front panel’s SMA connector). The
default clock source is
On Board
as shown in figure 33.
Figure 33 Reference Clock Status Display for default setting
If the external 10MHz clock input the chassis via SMA conncector, it will override the
onboard 10MHz clock. A phase-lock loop (PLL) circuit on the backplane synchronizes
the PXIe_CLK100 and external 10MHz clock, and then JYDM will display
Synchronized and green indicator as shown in figure 34.
Figure 34 Reference Clock Status Display for external clock source