11
3 Operations
This chapter contains information regarding analog input, triggering and timing for the PXIe-69852.
3.1 Functional Block Diagram
3�2 Analog Input Channel
3.2.1 Analog Input Front-End Configuration
Protection ckt
Calibration Source
AC / DC
Couple
High Impedance
Buffer
50 / Hi-Z
1x / 10x
amplifier
ADC Driver
100MHz
LPF
0
0
0
0
0
14
14-bit ADC
Figure 3-1: Analog Input Architecture of the PXIe-69852
Input Configuration
The input channel terminates with equivalent 50Ω or 1 MΩ input impedance (selected by software).
The 14-bit ADC provides not only accurate DC performance but also high signal- to-noise ratio, and
high spurious-free dynamic range in AC per- formance. The ADC transfers data to system memory via
the high speed PCI Express Gen2 X 4 interface.
For auto-calibration, internal calibration provides stable and accurate reference voltage to the AI.
3�2�2 Input Range and Data Format
Data format of the PXIe-69852 is 2’s complement. The ADC data of PXIe-69852 is on the 14 MSB
of the 16-bit A/D data. The 2 LSB of the 16-bit A/D data should be truncated by software. A/D data
structure is as follows.
