24
SSI_AD_TRIG
SSI_SYNC_START
SSI_TIMEBASE
SSI Interface
SSI Bus[0:7]
Timing Control
SSI Bus[0]
SSI Bus[5]
SSI Bus[1]
SSI_AD_TRIG
SSI_SYNC_START
Figure 3-10: SSI Architecture
Different signals cannot be routed onto the same trigger bus line.
The three internal timing signals can be routed to the SSI bus through software drivers.
Physically, signal routing is accomplished in the FPGA, with cards connected together
through the SSI bus achieving synchronization on the three timing signals, as follows.
3.6.1 SSI_TIMEBASE
As output, the SSI_TIMEBASE signal transmits the onboard ADC timebase through the
SSI bus. As input, the PCIe-69529 accepts the SSI_TIMEBASE signal as the source of the
timebase.
3�6�2 SSI_SYNC_START
Before a SSI master issues SSI_AD_TRIG to other SSI slaves, SSI_SYNC_START is first asserted
by the master card, synchronizing all on-chip ADCs in both SSI Master and SSI Slave modules.
3�6�3 SSI_AD_TRIG
As output, the SSI_AD_TRIG signal reflects the trigger event signal in an acquisition
sequence. As input, the PCIe-69529 accepts the SSI_AD_TRIG signal as the trigger event
source. The signal is configured in the rising edge-detection mode, with minimum pulse
width 20ns.
