PCIe/PXIe-5211 |
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4.5 Clocks
Figure 51 shows the structure of counter clock system.
Figure 51 Clocks Diagram
4.5.1 PLL
PLL (Phase Locked Loop) is a phase-locked clock generator that can generate a clock
signal of a specified frequency according to the selected reference clock source.
PCIe/PXIe
-
5211 Series boards support the following reference clock source:
1) Onboard 10MHz Clock
Using the on-board 10MHz (TXCO) as the PLL input source can help improve the PLL
output clock performance, including improving clock accuracy, temperature stability,
and phase noise.
2) PXIe_CLK100
The PXIe_CLK00 siganal is a 100MHz clock provided by the PXIe backplane for every
peripheral slot. When using this clock, PXIe-5211 can provide multi-card
synchronization.
3) External Reference Clock
An external reference clock is a clock provided by user through terminal
PXIe-DSTARA. To use an external reference clock, the user needs to specify its
frequency.
Содержание PCIe-5211
Страница 1: ...User Manual Version Revision Date V1 6 2 Oct 09 2021 PCIe PXIe 5211 Counter Timer Module User Manual...
Страница 9: ...PCIe PXIe 5211 jytek com 5 2 2 Digital IO Specifications Table 1 Digital IO Specifications...
Страница 10: ...PCIe PXIe 5211 jytek com 6 2 3 Counter Timer Specifications Table 2 Counter Timer Specifications...
Страница 11: ...PCIe PXIe 5211 jytek com 7 2 4 Other Specifications Table 3 Other Specifications...
Страница 12: ...PCIe PXIe 5211 jytek com 8 2 5 Front Panel and Pin Definition Figure 3 Front Pannel...
Страница 13: ...PCIe PXIe 5211 jytek com 9 Table 4 Pin Defination...
Страница 36: ...PCIe PXIe 5211 jytek com 32 Figure 24 Frequency Measure Values In Single Mode...