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3.4.4 PXI STAR Trigger
When you select PXI STAR as the trigger source, the PXI-69816/ PXI-69826/PXI-69846 can
accept a TTL-compatible digital signal as a trigger signal. The trigger occurs when a rising
edge or falling edge is detected at PXI STAR. You can use software to configure the trigger
polarity. The minimum pulse width requirement of this digital trigger signal is 20 ns.
3.4.5 PXI Trigger Bus
The PXI-69816/PXI-69826/PXI-69846 utilizes PXI Trigger Bus[0..7] as System Synchronization
Interface (SSI). Using the interconnected bus provided by PXI Trigger Bus, you can easily
synchronize multiple modules.
When configured as input, the PXI-69816/PXI-69826/PXI-69846 is served as a slave module
and can accept three different SSI signals, SSI_TRG1, SSI_TRG2 and SSI_START_OP. When
configured as output, the PXI-69816/PXI-69826/PXI-69846 is served as a master module
and can output SSI_TRG1, SSI_TRG2 or SSI_START_OP to PXI Trigger Bus. Each signal can
be routed from one of the PXI Trigger Bus[0..7] by software programming. For more detail
about these signals, please refer to Section “3.7” on page 34.
3.4.6 Trigger Signal Exporting
The PCI/PXI-69816/26/46 can export trigger signals to following connectors/bus: TRG IO on
front panel and PXI Trigger Bus[0..7].
The TRG IO on the front panel can also be programmed to output the trigger signal when
the trigger source is from software trigger, analog trigger, PXI STAR, or PXI Trigger Bus[0..7].
The timing characteristic is in Figure 3-10.
TRG IO
(Output)
Tw
Tw = 2 TIMEBASE Clocks
Figure 3-10: TRG IO Output Signal Timing
The PCI/PXI-69816/26/46 utilizes PXI Trigger Bus[0..7] as System Synchronize Interface.
When configured as output, the PCI/PXI-69816/26/46 is served as a master module and
can output 3 different trigger signals, SSI_TRG1, SSI_TRG2 and SSI_START_OP. You can route
these signals to any of PXI Trigger Bus[0..7] signals via software programming.