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T*AP
6
block diagram
The above schematic shows the principal blocks of the T*AP.
The core of the unit is the 10 channel Audio Processor with 2ch Aux inputs and a 2ch monitor output.
On the motherboard you will find 4x AES3id I/Os which are bridged by relays in case of a power failure.
Two I/O slots which may carry option boards allow for extremely flexible interfacing of the T*AP. I.e. you may
process the audio signals of two independent TV programs.
The unit may also be fitted with Dolby E/D/D+ decoder and encoder. For comprehensive metadata
processing the unit has serial metadata I/O connectors. All metadata functions are centralized in a metadata
Co-processor.
The sync circuit provides all features to integrate the T*AP into digital processing environments. Other
devices may be synchronized by the word clock output of the T*AP.
Beside the option to delay all DSP outputs, the T*AP has 4x 2Ch delay lines that may be routed into any
signal path of the device.