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5
µFlashTCP-EP User’s Manual
JK
microsystems
Hardware
Memory Configuration
The 386Ex processor is initially configured in real mode with a physical address space of 1
megabyte. The SRAM is located between 00000h and 7FFFFh, the flash is between 80000h and
FFFFFh. A 32-pin DIP socket is provided for additional flash, RAM, or EPROM. This memory
can be accessed by reprogramming the chip select unit in the 386Ex or by entering protected
mode.
During the boot process the BIOS is copied from flash into the top of RAM. The BIOS executes
out of RAM. After the BIOS is copied out of flash, the flash is removed from the memory map
with the exception of a small window near the 1 meg boundary. This allows the reset procedures
to work properly while maintaining user access to peripherals mapped in the higher portion of
memory. When a request for data on drive B: is processed, the flash is mapped in, the drive read,
then mapped out again. If present, the DiskOnChip occupies a block of memory starting at
segment E000 hex.
I/O Configuration
The 386Ex is configured for enhanced DOS mode. This mode provides access to the PC/AT
peripherals such as UARTs, counter/timers, and the interrupt controller at their traditional I/O
port addresses. Other 386Ex peripherals are accessible in expanded I/O space.
For addressing and programming the peripherals specific to the 386Ex, please refer to the Intel
386Ex Embedded Microprocessor User’s Manual (Intel document number 272485-002). The
manual is available in PDF format from our web site at http://www.jkmicro.com
Digital I/O Ports
The µFlashTCP-EP has 2 ports controlling a total of 10 bits of I/O.
386Ex Port 1 bits 4,5,6 and 7, I/O Address F860 and F862 hex
These signals are available on J5. The data on Port 1 can be read from I/O address F860 hex.
The default configuration is input. Each bit of Port 1 can be individually configured as an input
or output. To configure a bit for output, write a zero in that bit position to I/O address F864 hex.
To output data on Port 1, write the data to I/O address F862 hex.
P1PIN: F860h, Port Pin Status Register (read only), bits 4-7
P1LTC: F862h, Port Latch Register, bits 4-7
P1DIR: F864h, Port Direction Register, bits 4-7, 0 for output, 1 for input or open
drain output.
P1CFG: F820h, Port Configuration Register, bits 4-7 low, route P1.4-P1.7 to chip
pins (BIOS Default)
Hardware