ADwin
LS Bus, Manual version 1.0, September 2006
13
HSM-24V
LS_DIG_IO
ADwin
LS_DIG_IO
LS_DIG_IO
sets all digital outputs of the specified module HSM-24V on the LS
bus to the level High oder Low and returns the status of all channels as bit pat-
tern.
Syntax
#INCLUDE ADWL16.INC
ret_val = LS_DIG_IO
(
pattern
)
Parameters
Notes
LS_DIG_IO
only runs correctly, if the following conditions are given:
• There is only one module on the LS bus.
• The module is of type HSM-24V.
• The module's address is set to 1.
The channels are set as inputs or outputs using
LS_DIGPROG
.
The
pattern
is applied to those channels only, which are set as out-
puts. Bits for input channels are ignored.
The return value contains the real state of both inputs and outputs. The
inputs have a filter causing about 12µs signal delay.
LS_DIG_IO
resets the watchdog counter of the module to the start val-
ue. The counter remains enabled. The start value is set using
LS_
WATCHDOG_INIT
.
Reset the active watchdog timer at least once to the start value within
the counting interval, in order to keep the module working.
To be used for the modules
HSM-24V
See also
pattern
Bit pattern, setting the digital outputs (see table).
Bit = 0: Set outputs to level Low.
Bit = 1: Set outputs to level High.
ret_val
Bit pattern representing the real state of all digital
channels (see table).
Bit = 0: Channel has level Low.
Bit = 1: Channel has level High.
Bit No.
31
30
29
…
2
1
0
Input no.
32
31
30
…
3
2
1
LONG
LONG
