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i.MX8M SMARC SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
SMARC
Pin No. SMARC Edge
Signal Name
CPU Ball Name/
Pin Number
Signal Type/
Termination
Description
S125 MIPI_DSI_DATA0_P MIPI_DSI_DATA0_P/
B17 O, MIPI MIPI DSI0 differential data
lane 0 positive.
S126 MIPI_DSI_DATA0_N MIPI_DSI_DATA0_N/
A17 O, MIPI MIPI DSI0 differential data
lane 0 negatives.
S127 GPIO_LCD0_1_EN(GPIO3_17) NAND_WE_B/
K22 O, 1.8V CMOS LCD0 Backlight Enable.
S128 MIPI_DSI_DATA1_P MIPI_DSI_DATA1_P/
B16 O, MIPI MIPI DSI0 differential data
lane 1 positive.
S129 MIPI_DSI_DATA1_N MIPI_DSI_DATA1_N/
A16 O, MIPI MIPI DSI0 differential data
lane 1 negative.
S131 MIPI_DSI_DATA2_P MIPI_DSI_DATA2_P/
B18 O, MIPI MIPI DSI0 differential data
lane 2 positive.
S132 MIPI_DSI_DATA2_N MIPI_DSI_DATA2_N/
A18 O, MIPI MIPI DSI0 differential data
lane 2 negatives.
S133 GPIO_LCD0_VDD_EN(GPIO3_18) NAND_WP_B/
K21 O, 1.8V CMOS LCD0 Power Enable.
S134 MIPI_DSI_CLK_P MIPI_DSI_CLK_P/
D16 O, MIPI MIPI DSI0 differential
Clock positive.
S135 MIPI_DSI_CLK_N MIPI_DSI_CLK_N/
C16 O, MIPI MIPI DSI0 differential
Clock negative.
S137 MIPI_DSI_DATA3_P MIPI_DSI_DATA3_P/
B15 O, MIPI MIPI DSI0 differential data
lane 3 positive.
S138 MIPI_DSI_DATA3_N MIPI_DSI_DATA3_N/
A15 O, MIPI MIPI DSI0 differential data
lane 3 negative.
S139 I2C4_SCL I2C4_SCL/
F8 O, 1.8V CMOS I2C CLK for Display and
Touch.
S140 I2C4_SDA I2C4_SDA/
F9 IO, 1.8V CMOS I2C DATA for Display and
Touch.
S141 GPIO_LCD0_BL_PWM(GPIO1_14) GPIO1_IO14/
K7
O, 1.8V CMOS LCD0 Back Light Brightness
control PWM.
2.7.8 Audio Interface
The i.MX8M SMARC SOM supports I2S0 and I2S1 channels of SMARC Edge connector from CPU’s SAI 2 and SAI3
channels respectively. The SAI peripheral provides a synchronous audio interface that supports full duplex serial
interfaces with frame synchronization such as I2S, AC97 and other audio CODEC/DSP interfaces. The SAI general
features are including Transmitter section with independent bit clock and frame sync, Maximum frame size of 32
words, Word size from 8-bits to 32-bits and Supports graceful restart after FIFO error. Only Transmitter CK and LRCK
is supported as per SMARC specification.
In i.MX8M SMARC SOM the transmitter is configured for asynchronous mode and the receiver is configured for
synchronous mode, hence both transmitter and receiver will use the transmitter bit clock and frame sync.
For more details on SMARC Edge I2S pinouts on SAMRC Edge connector, refer below table: