REL 1.0
Page 36 of 89
RZ/G1M/G1N Qseven Development Platform Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.6
High Speed Interface Features
2.6.1
USB3.0 Port0 (Host)
The RZ/G1M/G1N Qseven carrier board supports Super Speed USB3.0 Host interface through RZ/G1M/G1N CPU’s
USB3.0 interface. This USB3.0 Port0 signals of Qseven MXM connector is directly connected to bottom port of dual
stack USB3.0 TypeA connector (J23). Also USB2.0 Port2 signals of Qseven MXM connector is connected to this
connector for USB2.0 host interface from RZ/G1M/G1N CPU’s USB1 interface.
The VBUS power of this USB3.0 connector is connected through current limit power switch and limit is set as 900mA.
If connected USB3.0 device takes more than 900mA current, this power switch limits the current to constant mode
and sends the over current indication signal to the over current indicator pin of Qseven MXM connector USB port 6
& 7. This USB3.0 connector is physically located at the top of the board as shown below.
Figure 8: USB3.0 Host Port0
Table 6: Dual stack USB 3.0 Connector Pin Out (Bottom port)
Pin
No
Pin Name
Signal Name
Signal Type/
Termination
Description
1
VCC_5V
VBUS
O, 5V Power
5V Supply Voltage.
2
USB_DM
USB_P2-
IO, DIFF
USB2.0 Host Port2 data negative.
3
USB_DP
IO, DIFF
USB2.0 Host Port2 data positive.
4
GND
GND
Power
Ground.
5
USB_RXN
USB3_RXN
IO, DIFF
USB3.0 Host Port0 Receive pair negative.
6
USB_RXP
USB3_RXP
IO, DIFF
USB3.0 Host Port0 Receive pair positive.
7
GND
GND
Power
Ground.
8
USB_TXN
USB3_TXN
IO, DIFF
USB3.0 Host Port0 Transmit pair negative.
9
USB_TXP
USB3_TXP
IO, DIFF
USB3.0 Host Port0 Transmit pair positive.