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i.MX6UL/i.MX6ULL SODIMM SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.6.10 I2C Interface
i.MX6UL/i.MX6ULL SODIMM SOM supports one I2C interface on SODIMM Edge connector. i.MX6UL/i.MX6ULL CPU’s
I2C1.channel is used for General purpose I2C interface which is compatible with the standard NXP I2C bus protocol. It
supports standard mode with data transfer rates up to 100kbps and Fast mode with data transfer rates up to 400kbps.
Since flexible I2C standard allows multiple devices to be connected to the single bus, i.MX6UL/i.MX6ULL CPU’s I2C1
can be connected to more than one device on the carrier board. This I2C1 interface is also connected to On-SOM PMIC
with I2C address 0x08 in the i.MX6UL/i.MX6ULL SODIMM SOM.
For more details, refer SODIMM Edge connector pins 115 & 116 on Table 5.
2.6.11 PWM Interface
i.MX6UL/i.MX6ULL SODIMM SOM supports two PWM interface on SODIMM Edge connector. i.MX6UL/i.MX6ULL CPU’s
PWM4 and PWM5 module is used for PWM interface which has a 16-bit counter and optimized to generate sound
from stored sample audio images and it can also generate tones. It uses 16-bit resolution and a 4 x 16 data FIFO.
For more details, refer SODIMM Edge connector pins 138 & 147 on Table 5.
2.6.12 Tamper Interface
i.MX6UL3 SODIMM SOM supports upto seven external Tamper detection signals on SODIMM Edge connector. External
Tamper Detection is a special mechanism provided through i.MX6UL3 CPU pin to signal when the device encounters
unauthorized opening or tampering. Inside the i.MX6UL3 CPU, the received signal is compared with the desired signal
level, once unequal, tamper event is found. An always-ON power supply (coin cell battery) should be present in the
system.
For more details, refer SODIMM Edge connector pins 47, 68, 73, 86, 133, 134 & 136 on Table 5.
Important Note: Only i.MX6UL3 version CPU supports tamper functionality on these pins and doesn’t support GPIO
functionality. For all other i.MX6UL/i.MX6ULL CPU versions, these tamper pins are used as only GPIOs.
2.6.13 GPIO Interface
Most of the i.MX6UL/i.MX6ULL CPU Pins which are connected to SODIMM Edge connector can be configured as GPIO
with interrupt capable (if not used as other interface). i.MX6UL/i.MX6ULL CPU GPIO controller provides dedicated
general-purpose pins that can be configured as either inputs or outputs. When configured as an output, it is possible
to write to an internal register to control the state driven on the output pin. When configured as an input, it is possible
to detect the state of the input by reading the state of an internal register. In addition, the GPIO peripheral can produce
Core interrupts.