REL 1.2
Page 44 of 82
i.MX6 Qseven PMIC SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.8.4
ESAI Interface
i.MX6 Qseven PMIC SOM supports one ESAI interface on Expansion connector1. i.MX6 CPU’s ESAI module is used for
ESAI interface which provides a full-duplex serial port for serial communication with a variety of serial devices,
including industry-standard codecs, SPDIF transceivers and other DSPs. The ESAI features independent
(asynchronous mode) or shared (synchronous mode) transmit and receive sections with separate or shared
internal/external clocks and frame syncs operating in Master or Slave mode.
It supports up to six transmitters and four receivers with TX2_RX3, TX3_RX2, TX4_RX1, and TX5_RX0 pins shared by
transmitters 2 to 5 and receivers 0 to 3. TX0 and TX1 pins are used by transmitters 0 and 1 only. It has 128-word
Transmit FIFO shared by six transmitters and 128-word Receive FIFO shared by four receivers. It also supports
programmable data interface modes (such as I2S, LSB aligned, MSB aligned) and programmable word length (8, 12,
16, 20 or 24bits).
For more details, refer Expansion connector1 pins 3,5,7 to 14, 16 & 18 on
2.8.5
SPDIF Interface
i.MX6 Qseven PMIC SOM supports one SPDIF interface on Expansion connector1. i.MX6 CPU’s SPDIF module is used
for SPDIF interface which is a stereo transceiver that allows the processor to receive and transmit digital audio over
it using the IEC60958 standard. It is composed of SPDIF Receiver with one input & SPDIF Transmitter with one output
and allows the handling of both SPDIF channel status (CS) and User (U) data.
The SPDIF receiver extracts the audio data from each SPDIF frame and places the data in the SPDIF Rx left and right
FIFOs. The SPDIF transmitter generates a SPDIF output bit stream in the biphase mark format (IEC60958), which
consists of audio data, channel status and user bits.
For more details, refer Expansion connector1 pins 15 & 17 on
2.8.6
Data UART Interface (UART1 & UART3)
i.MX6 Qseven PMIC SOM supports two Data UART interface on Expansion connector1 along with one more on
Qseven Edge connector and one more on Expansion connector2. i.MX6 CPU’s UART1 and UART3 controller is used
for Data UART interface on Expansion connector1 which supports Serial RS-232NRZ mode, 9-bit RS-485 mode and
IrDA mode. It is compatible with High-speed TIA/EIA-232-F (up to 5.0 Mbit/s) with auto baud rate detection (up to
115.2 Kbit/s). It supports 7 or 8 data bits for RS-232 characters (9 bit RS-485 format), 1 or 2 stop bits and
programmable parity (even, odd, and no parity). Also i.MX6 Qseven PMIC SOM supports hardware flow control for
request to send and clear to send signals.
For more details, refer Qseven Edge connector pins 51 to 54 & 61 to 64 on