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IGEP

SMARC iMX6

Hardware Reference Manual

NIF:ESB64377005 Document:

MAN-IGEP0046-001

/ Revision:

1.3

/ Date:

23/06/2016

4.17

MIPI DSI

The Display Serial Interface (DSI) is a specification by the

Mobile Industry Processor Interface

(MIPI) Alliance

aimed at reducing the cost of

display controllers

in a

mobile device

. It is commonly targeted at

LCD

and

similar display technologies. It defines a

serial bus

and a communication protocol between the host (source of

the image data) and the device (destination of the image data).

SMARC does not define MIPI DSI output, but in IGEP

SMARC iMX6 is connected to S68, S69, S71, S72, S74

and S75 pins as next table show.

Pin

Volt

Level

Dev

Pin

Main Function

Main
MUX

Type

Fixed

Function

Comments

S68

DIF

MIPI DSI 1.01

YES

DSI differential clock +

S69

DIF

AFB_DIFF2-

MIPI DSI 1.01

YES

DSI differential clock -

S71

DIF

MIPI DSI 1.01

YES

DSI differential data D0 +

S72

DIF

AFB_DIFF3-

MIPI DSI 1.01

YES

DSI differential data D0 -

S74

DIF

MIPI DSI 1.01

YES

DSI differential data D1 +

S75

DIF

AFB_DIFF4-

MIPI DSI 1.01

YES

DSI differential data D1 -

Table 21 MIPI DSI pins

4.18

LVDS

The next figure show how to connect LVDS display signals to connector (page 32 of SMARC Design Guide
V_IO=1V8).

Figure 26 LVDS connection example

Pin

Volt

Level

Dev

Pin

Main Function

Main
MUX

Type

Fixed

Function

Comments

S125

DIF

LVDS0+

LVDS TIA/EIA-644

YES

LVDS data channel differential pair D0 +

S126

DIF

LVDS0-

LVDS TIA/EIA-644

YES

LVDS data channel differential pair D0 -

S128

DIF

LVDS1+

LVDS TIA/EIA-644

YES

LVDS data channel differential pair D1 +

S129

DIF

LVDS1-

LVDS TIA/EIA-644

YES

LVDS data channel differential pair D1 -

S131

DIF

LVDS2+

LVDS TIA/EIA-644

YES

LVDS data channel differential pair D2 +

S132

DIF

LVDS2-

LVDS TIA/EIA-644

YES

LVDS data channel differential pair D2 -

S134

DIF

LVDS TIA/EIA-644

YES

LVDS clock channel differential pair +

S135

DIF

LVDS_CK-

LVDS TIA/EIA-644

YES

LVDS clock channel differential pair -

S137

DIF

LVDS3+

LVDS TIA/EIA-644

YES

LVDS data channel differential pair D3 +

S138

DIF

LVDS3-

LVDS TIA/EIA-644

YES

LVDS data channel differential pair D3 -

Table 22 LVDS pins

Содержание IGEP SMARC iMX6

Страница 1: ...on 1 3 Date 23 06 2016 ISEE Integration Software Electronics Engineering c Marcos Redondo 5 Valldoreix E08197 Sant Cugat del Vall s SPAIN 34 93 5763931 info iseebcn com https www isee biz IGEP TM SMAR...

Страница 2: ...APPLICATIONS 7 2 3 The IGEPTM SMARC iMX6 SERIES 7 2 4 ORDERING INFORMATION 8 2 5 EXPANSION BOARDS 8 3 OVERVIEW 9 3 1 IGEPTM SMARC iMX6 9 3 2 IGEPTM SMARC iMX6 FEATURES 10 3 3 IGEPTM SMARC iMX6 VARIANT...

Страница 3: ...30 4 15 PCIe 31 4 16 MIPI CSI 32 4 17 MIPI DSI 33 4 18 LVDS 33 4 19 HDMI 34 4 20 SUPERVISOR 35 4 21 ENVIRONMENTAL SPECIFICATION 35 4 22 STANDARDS AND CERTIFICATIONS 35 4 23 MTBF 36 4 24 MECHANICAL SP...

Страница 4: ...nfringements upon the rights of third parties which may result from its use 1 3 TRADEMARKS IGEPTM istrademark of ISEE ISEE is trademark or registered trademark of ISEE 2007 SL Product names logos bran...

Страница 5: ...tual property right of ISEE covering or relating to any machine process or combination in which such ISEE products or services might be or are used NOTE It could be found a detailed warranty and sales...

Страница 6: ...to complement the module It s a developer baseboard and it can be used as the fastest way to test the final application before the prototyping phase Highlights Fully tested highly reliable scalable e...

Страница 7: ...Commercial and Industrial Temperature Range 0 C to 60 C and 40 C to 85 C Extended life range product min 10 years At the same time it can be implemented in all kind of end applications The followings...

Страница 8: ...EPTM SMARC iMX6DualLite IGEP SMARC iMX6DL 1G 4G W E Processor iMX6 DualLite RAM Memory 1 GB DDR3 SDRAM Storage 4GB eMMC IGEPTM SMARC iMX6Dual IGEP SMARC iMX6D 2G 8G W E Processor iMX6 Dual RAM Memory...

Страница 9: ...is a registered trademark from ISEE 2007 S L The following is provided for informational purposes only NIF ESB64377005 Document MAN IGEP0046 001 Revision 1 3 Date 23 06 2016 9 3 OVERVIEW 3 1 IGEPTM SM...

Страница 10: ...core L2 cache 512 KB NEONTM SIMD Coprocessor per core PTM per core 1x NXP iMX6 ARM Cortex A9TM up to 1GHz L1 Instruction cache 32 KB L1 Data cache 32 KB L2 cache 512 KB NEONTM SIMD Coprocessor PTM 2D...

Страница 11: ...IEEE 802 11 a b g n with Access Point 1 x Bluetooth v4 0 1 x SPI NOR flash 1 x EEPROM Table 6 On board interfaces and devices 3 3 IGEPTM SMARC iMX6 VARIANTS The IGEPTM SMARC iMX6 modules are based in...

Страница 12: ...MAN IGEP0046 001 Revision 1 3 Date 23 06 2016 12 3 4 iMX6 ARM CORTEX A9 PROCESSORS The iMX6 by NXP are a family of highly integrated microprocessors based on the ARM Cortex A9 processor They have a h...

Страница 13: ...EP is a registered trademark from ISEE 2007 S L The following is provided for informational purposes only NIF ESB64377005 Document MAN IGEP0046 001 Revision 1 3 Date 23 06 2016 13 4 PRODUCT SPECIFICAT...

Страница 14: ...schematic example of this power signal page 88 of SMARC Design Guide Figure 6 Power Supply Input circuit RTC Battery The RTC Battery pin S147 allows the connection of a battery With this in case of a...

Страница 15: ...e can be fixed by user acting over the pins P125 P124 and P123 When the module is powered on it reads these pins and it boots as it is specified in next table BOOT_SEL2 P125 BOOT_SEL2 P124 BOOT_SEL2 P...

Страница 16: ...other one is a RESET_OUT P126 When the RESET_IN is driven to Low state with a delay configurable the power supply from the Power Management IC PMIC is turned off The RESET_OUT pin is an output signal...

Страница 17: ...circuitry to maintain the signal integrity Moreover the magnetics module has a critical effect so it has to be designed carefully In order to obtain a smaller size it s usual to use RJ45 connectors w...

Страница 18: ...fferential output to magnetics P27 DIF NC GBE_MDI1 NA ETH YES Analog Transmit Receive Data 1 Positive Differential output to magnetics P23 DIF NC GBE_MDI2 NA ETH YES Analog Transmit Receive Data 2 Neg...

Страница 19: ...The SMARC 314 connector lines referred to this function are adapted for a USB type A receptacle see wiring example in the next figure page 65 of SMARC Design Guide Figure 12 USB 2 0 Host connections...

Страница 20: ...To protect the VBUS against overcurrent the USB power source current have to be less or equal than 500mA and the user must provide a protection in the base board as it is showed into Figure 12 USB 2...

Страница 21: ...ge 46 of SMARC Design Guide V_IO 1V8 Figure 14 I2C example EEPROM connection Pin Volt Level Dev Pin Main Function Main MUX Type Fixed Function Comments 1ST I2C S5 1V8 H20 I2C_CAM_CK 6 IO YES I2C1 bus...

Страница 22: ...eripheral with 16 bits time base with Period and Frequency control and two outputs Max PWM frequency is 66 MHz More information at chapter 52 from iMX6 Applications Processor Reference Manual In the n...

Страница 23: ...a SPI NOR flash is connected through SPI3 and SPI3_CS0 it is optional In the next figure an example is shown to connect the IGEPTM SMARC iMX6 module to an SPI Flash Socket page 58 of SMARC Design Gui...

Страница 24: ...d into on board eMMC flash The next example shows how to connect a uSD card reader to SDIO pins page 78 of SMARC Design Guide Figure 17 MMC example uSD card reader Pin Volt Level Dev Pin Main Function...

Страница 25: ...devices or debug via serial They are available in the SMARC 314 in three blocks of pins The IGEPTM SMARC iMX6 uses a 1V8 voltage levels for UART buses In some cases voltage translators should be nece...

Страница 26: ...19 RS485 example RS485 circuit Pin Volt Level Dev Pin Main Function Main MUX Type Fixed Function Comments 1ST UART P134 1V8 E24 SER1_TX 4 OUT NO Debug UART2 Transmit Data Output P135 1V8 E25 SER1_RX 4...

Страница 27: ...ta bus using shielded or unshielded twisted differential pair wiring with an impedance termination of 120 at the endpoints of the bus Nodes on the bus are arranged in daisy chain fashion A CAN Transce...

Страница 28: ...master a left right clock output from the master that indicates the channel being transmitted and a single bidirectional data line or two data lines one input and one output A SMARC module can general...

Страница 29: ...1V8 N1 GPIO0 5 IO NO General purpose input output GPIO5_IO22 P109 1V8 P2 GPIO1 5 IO NO General purpose input output GPIO5_IO23 P110 1V8 N4 GPIO2 5 IO NO General purpose input output GPIO5_IO24 P111 1...

Страница 30: ...coupling capacitors are defined in the SMARC specification to be on the Module for both SATA transmit and receive pairs The next figure show how to connect SATA SMARC pins to mSATA connector page 77...

Страница 31: ...Figure 24 PCIe connection example Pin Volt Level Dev Pin Main Function Main MUX Type Fixed Function Comments P83 DIF D7 PCIE_A_REFCK 0 LVDS TIA EIA 644 YES Differential PCIe Link A reference clock ou...

Страница 32: ...Dev Pin Main Function Main MUX Type Fixed Function Comments P3 DIF F3 CSI1_CK 0 MIPI CSI 2 YES CSI1 differential clock input P4 DIF F4 CSI1_CK 0 MIPI CSI 2 YES CSI1 differential clock input P7 DIF E3...

Страница 33: ...F G2 AFB_DIFF3 0 MIPI DSI 1 01 YES DSI differential data D0 S74 DIF H1 AFB_DIFF4 0 MIPI DSI 1 01 YES DSI differential data D1 S75 DIF H2 AFB_DIFF4 0 MIPI DSI 1 01 YES DSI differential data D1 Table 21...

Страница 34: ...1V8 Figure 27 HDMI connection example Pin Volt Level Dev Pin Main Function Main MUX Type Fixed Function Comments P92 DIF K4 HDMI_D2 0 HDMI 1 4a YES HDMI data differential pair D2 P93 DIF K3 HDMI_D2 0...

Страница 35: ...are available for industrial grade temperature range The operating temperature is the maximum measurable temperature on any spot on the module s surface Humidity o 93 relative Humidity at 40 C non co...

Страница 36: ...C form factor standard The SMARC Smart Mobility ARChitecture is a versatile small form factor computer Module definition targeting applications that require low power low costs and high performance ht...

Страница 37: ...NICAL SPECIFICATION Module Dimension o 82 mm x 50 mm x 4 mm Mechanical Drawing The next figures show the IGEPTM SMARC iMX6 modules mechanical dimensions o All dimensions are in millimeters o 8 layer P...

Страница 38: ...Ds D1300 and D1301 GPIO controlled JTAG 11pin 1 25mm pitch interface J1300 SMARC 314 314 pin SMARC interface J900 Expand many functionalities from iMX6 processor Table 25 Interface summary 5 2 LEDs Th...

Страница 39: ...G connector schematic Note that even pins are left unconnected but the footprint makes possible to use a 11 pin 1 27 mm pitch connector The next table details the signals on each pin of J1300 Signal N...

Страница 40: ...314 EXPANSION CONNECTOR INTERFACE The IGEPTM SMARC iMX6 has 1 SMARC 314 interface J900 composed by 314 metal contacts 156 on TOP side and 158 on BOTTOM side providing source power and 1V8 CMOS signal...

Страница 41: ...2016 41 The IGEPTM SMARC iMX6 modules can be inserted like a target through this SMARC 314 interface to any of the standard SMARC 314 connectors existing on the market Some valid references are MANUFA...

Страница 42: ...UX Mode number for the main function TYPE Indicates pin type POWER Power signal IN CMOS input pin OUT CMOS output pin IO CMOS input and output pin ETH Ethernet physical pin USB USB line NC No connecte...

Страница 43: ...D NC DGND NA POWER YES Digital Ground P16 CSI1_D3 PCAM_D8 DIF F1 CSI_DATA3_P 0 MIPI CSI 2 YES CSI1 differential data input D3 P17 CSI1_D3 PCAM_D9 DIF F2 CSI_DATA3_N 0 MIPI CSI 2 YES CSI1 differential...

Страница 44: ...GND GND NC DGND NA POWER YES Digital Ground P51 SATA_RX DIF B14 SATA_PHY_RX_P 0 SATA 3 Gb s YES Differential SATA receive data This signal has a 10 nF coupling capacitor P52 SATA_RX DIF A14 SATA_PHY_R...

Страница 45: ...LVDS TIA EIA 644 YES Differential PCIe Link A receive data pair 0 P87 PCIE_A_RX DIF B1 PCIE_RX_N 0 LVDS TIA EIA 644 YES Differential PCIe Link A receive data pair 0 P88 GND GND NC DGND NA POWER YES Di...

Страница 46: ...P118 GPIO10 1V8 R21 GPIO4_IO31 5 IO NO General purpose input output P119 GPIO11 1V8 T23 GPIO5_IO05 5 IO NO General purpose input output P120 GND GND NC DGND NA POWER YES Digital Ground P121 I2C_PM_CK...

Страница 47: ...D_IN 5V NC VIN NA POWER YES P155 VDD_IN 5V NC VIN NA POWER YES P156 VDD_IN 5V NC VIN NA POWER YES S1 PCAM_VSY NC NC NC No connected NA NC NC No connected S2 PCAM_HSY NC NC NC No connected NA NC NC No...

Страница 48: ...O AUD4 Data Transmit signal S41 I2S0_SDIN 1V8 W24 AUD4_RXD 3 IN NO AUD4 Data Receive signal S42 I2S0_CK 1V8 U22 AUD4_TXC 3 IO NO AUD4 Transmit Clock signal S43 I2S1_LRCK NC NC No connected NA NC NC No...

Страница 49: ...NC No connected NA NC NC No connected S83 GND GND NC DGND NA POWER YES Digital Ground S84 PCIE_B_REF CK NC NC No connected NA NC NC No connected S85 PCIE_B_REF CK NC NC No connected NA NC NC No connec...

Страница 50: ..._ EN 1V8 M6 GPIO6_IO04 5 IO NO High enables panel backlight S128 LVDS1 DIF U3 LVDS0_DATA1_P 0 LVDS TIA EIA 644 YES LVDS data channel differential pair D1 S129 LVDS1 DIF U4 LVDS0_DATA1_ N 0 LVDS TIA EI...

Страница 51: ...TION NA IN YES Power bad indication from Carrier board S151 CHARGING 1V8 M5 GPIO6_IO01 5 IN YES Held low by Carrier during battery charging This signal has a 3K3 PU resistor S152 CHARGER_ PRSNT 1V8 N1...

Страница 52: ...nput output Low Level DC voltage 0 5 0 0 54 V Output drive current 0 1 0 5 1 mA RTC_BATTERY type pins Input DC voltage 2 5 3 3 3 V Table 31 IGEPTM SMARC iMX6 Electrical characteristics 1 Current measu...

Страница 53: ...26 Table 15 CAN pins 27 Table 16 I2S pins 28 Table 17 GPIO pins 29 Table 18 SATA pins 30 Table 19 PCIe pins 31 Table 20 MIPI CSI pins 32 Table 21 MIPI DSI pins 33 Table 22 LVDS pins 33 Table 23 HDMI p...

Страница 54: ...Headphone AMP 28 Figure 22 GPIOs example control circuit to manage LEDs 29 Figure 23 SATA connection example 30 Figure 24 PCIe connection example 31 Figure 25 MIPI CSI connection example 32 Figure 26...

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