IGEP
TM
SMARC iMX6
Hardware Reference Manual
ISEE 2007 S.L. All rights reserved, IGEP is a registered trademark from ISEE 2007 S.L. The following is provided for informational purposes only.
NIF:ESB64377005 Document:
MAN-IGEP0046-001
/ Revision:
1.3
/ Date:
23/06/2016
23
4.8
SPI: SERIAL PERIPHERAL INTERFACE
The Serial Peripheral Interface (SPI) is one more of the different possibilities to connect the module to
external peripherals. It’s a full duplex synchronous bus, supporting a single master and up to two slave devices
each SPI peripheral.
The IGEP
TM
SMARC iMX6 uses a 1V8 voltage levels for SPI buses. In some cases, voltage translators should be
necessary to adapt voltage levels between ICs. It is important to say that a SPI NOR flash is connected
through SPI3 and SPI3_CS0 (it is optional).
In the next figure an example is shown to connect the IGEP
TM
SMARC iMX6 module to an SPI Flash Socket
(page 58 of SMARC Design Guide V_IO=1V8).
Figure 16 SPI example: SPI Flash Socket
Pin
Volt
Level
Dev
Pin
Main Function
Main
MUX
Type
Fixed
Function
Comments
P31
1V8
R25
SPI0_CS1#
2
OUT
NO
SPI3 chip select 2 signal
P43
1V8
P20
SPI0_CS0#
2
OUT
NO
SPI3 chip select 1 signal
P44
1V8
P24
SPI0_CK
2
OUT
YES
SPI3 clock
P45
1V8
P23
SPI0_DIN
2
IN
YES
SPI3 Master Input-Slave Output (MISO)
P46
1V8
P22
SPI0_DO
2
OUT
YES
SPI3 Master Output-Slave Input (MOSI)
P54
1V8
V25
SPI1_CS0#
2
OUT
NO
SPI2 chip select 0 signal
P55
1V8
T22
SPI1_CS1#
2
OUT
NO
SPI2 chip select 1 signal
P56
1V8
H24
SPI1_CK
2
OUT
NO
SPI2 clock
P57
1V8
J24
SPI1_DIN
2
IN
NO
SPI2 Master Input-Slave Output (MISO)
P58
1V8
J23
SPI1_DO
2
OUT
NO
SPI2 Master Output-Slave Input (MOSI)
Table 12 SPI pins
