background image

1

 Application Note 1664

ISL97683 LED Driver Evaluation Board User Manual

Introduction

The ISL97683 Evaluation Board provides a complete testing 
platform for ISL97683, a three channel LED driver. Please 
refer to the product datasheet for detailed information, 
including pinout, pin function descriptions, electrical 
specifications and applications related information.

Instructions

Please follow the steps described below to start your 
evaluation.

1. Set Switch #1 and Switch #2 (SW1 and SW2) to position 3 

(left side).

2. For the enable control jumper, JP1, set the shunt to the 

“ON” position (right side) to connect the EN pin to VIN. 
When the shunt is in the “OFF” position, it will disable the 
chip by pulling the EN pin to ground.

3. Connect JP14 so the VIN pin is connected to PVIN.
4. For JP20, connect the shunt to the upper position.
5. Connect WR and JP2-JP6.
6. Apply 1.5V~5.5V PWM signal between the PWMI pin and 

AGND.

7. Apply 4V~26.5V between PVIN and PGND and the LEDs 

should be lit. You may start the evaluation.

Note:
• In Step #1 above, the SW1, SW2 position can be adjusted to 

different positions for different configurations. Details are 
provided in the following:

• The LED maximum DC current adjustment

For each channel, the maximum DC current is set by 
resistance connected to the RSET pin. The current for each 
channel can be calculated as follows: 

On the board, a potentiometer R5 and a few other resistors 
are provided for easily adjusting the LED maximum DC 
current; please refer to the evaluation board schematic on 
page 2 for more details.

• LED dimming frequency and duty cycle

1. As mentioned in Step #4, when the shunt on JP20 is 

connected to the upper position and  the FPWM/DPWM pin 
is connected to VDC, the device enters direct PWM mode, 
which means both the LED dimming frequency and the 
duty cycle are synchronized with the external PWM signal 
applied on the PWMI pin.

2. When the shunt on JP20 is connected to the lower position, 

the FPWM/DPWM pin is connected to a resistor. Under 
such conditions, the LED dimming frequency of the chip is 
programmed by the resistance connected on the 
FPWM/DPWM pin per the following equation:

The duty cycle is still modulated by the external PWM signal 
applied on the PWMI pin. On board, a potentiometer R11 
and a few other resistors are provided for easily adjusting 
the LED dimming frequency under such configuration.

TABLE 1.

SW1 

POSITION

SW2 

POSITION

DESCRIPTION

1

1

LX switching frequency = 600kHz, PFM  
CH1-CH3

3

3

LX switching frequency = 1MHz, PFM  
CH1-CH3

3

1

LX switching frequency = 600kHz, No PFM  
CH1-CH3

1

3

LX switching frequency = 1MHz, No PFM  
CH1-CH3

I_LED(mA)

402 RSET

k

Ω

=

(EQ. 1)

FPWM Hz

(

)

12.4

7

×

10

R_FPWM

Ω

( )

=

(EQ. 2)

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

|

Copyright Intersil Americas Inc. 2011. All Rights Reserved

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

December 13, 2011
AN1664.0

Содержание ISL97683

Страница 1: ...asily adjusting the LED maximum DC current please refer to the evaluation board schematic on page 2 for more details LED dimming frequency and duty cycle 1 As mentioned in Step 4 when the shunt on JP20 is connected to the upper position and the FPWM DPWM pin is connected to VDC the device enters direct PWM mode which means both the LED dimming frequency and the duty cycle are synchronized with the...

Страница 2: ...nF 50V R5 1M R6 0 R7 Open R8 5k R9 10k C15 8 2nF C3 33pF TP1 LX TP2 VOUT TP3 CH1 TP4 CH2 TP5 CH3 TP7 VDC P5 AGND P6 AGND P7 AGND P8 AGND P9 PGND P10 PGND 2 layer board Connect top layer PGND and bottom layer AGND at one single point through the via on the thermal pad under the chip F1 2A Fuse JP14 R11 100k R10 0 R13 Open R12 27k JP15 JP16 JP17 ISL97683EVAL1Z Rev A EN can be connected in the follow...

Страница 3: ...Application Note 1664 3 AN1664 0 December 13 2011 PCB Layout FIGURE 2 TOP SILKSCREEN LAYER AND TOP LAYER ...

Страница 4: ...Application Note 1664 4 AN1664 0 December 13 2011 FIGURE 3 BOTTOM LAYER PCB Layout Continued ...

Страница 5: ... X7R capacitors C3 33pF 603 C4 1µF 16V 603 C5 4 7µF 50V 1210 Murata GRM32ER71H475KA88L C6 4 7µF 50V 1210 C7 Place Holder 1210 Not Populated C8 Place Holder 1210 C9 100pF 50V 603 General purpose C10 3 6nF 50V 603 Ceramic X5R X7R capacitors C11 1nF 50V 603 C12 1nF 50V 603 C13 1nF 50V 603 C14 Place Holder 603 C15 8 2nF 603 F1 2A Fuse 1206 Bel Fuse Inc C1Q 2 U1 QFN16 3MM Intersil ISL97682 3 4 JP2 JP19...

Страница 6: ...l com AN1664 0 December 13 2011 TP3 CH1 TEST POINT TP4 CH2 TEST POINT TP5 CH3 TEST POINT TP6 CH4 TEST POINT TP7 VDC TEST POINT TP8 RSET TEST POINT TP9 FSW PHS TEST POINT P5 AGND TEST POINT Keystone Electronics P6 AGND TEST POINT 5011 P9 PGND TEST POINT P1 PVIN POWERPOST Mill Max P2 VIN POWERPOST 3156 1 00 00 00 00 08 0 P3 EN POWERPOST P4 PWMI POWERPOST P7 AGND POWERPOST P8 AGND POWERPOST P10 PGND ...

Отзывы: