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ISL6227EVAL1 DDR Evaluation Board Setup

Procedure

This document describes the setup procedure for the 
ISL6227 Evaluation Board DDR implementation. For 
information about the dual switcher application, please refer 
to the ISL6227EVAL2 Evaluation Board Setup Procedure.

General Description

The ISL6227 can control two output voltages adjustable from 

0.9V to 5.5V. The ISL6227 combines two synchronous PWM 

voltage regulators into a single IC. When the DDR pin is set 

to high, it transforms the IC into a complete DDR application.
Channel 1 can be set at a fixed 300kHz forced PWM mode or 

an automatic mode with hysteretic diode-emulation at light 

load and constant-frequency PWM synchronous rectification 

at heavy load, assure high efficiency over a wide range of 

conditions. Channel 2 is set at fixed 300kHz forced PWM 

mode with synchronous rectification because of sinking 

current requirement for DDR applications. Both channels use 

the lower MOSFET r

DS(ON)

 as the current sense element for 

high efficiency operations. It is preferred that the input of the 

second channel connects to the output of the first channel in 

DDR applications.
Voltage-feed-forward ramp modulation, current mode control, 

and internal feedback compensation provide fast response to 

input voltage and output load transients.
ISL6227 monitors the output voltage of CH1 only by the 

voltage on VSEN1 pin. PGOOD1 (power good) signal is 

asserted after its soft-start sequence has completed, and the 

output voltage within -11%/+15% of the set point. PGOOD2 

pin is used to bring the VDDQ/2 into the chip as the 

reference voltage of the second channel error amplifier.
Built-in overvoltage protection prevents the output from 

going above 115% of the set point by holding the lower 

MOSFET on and the upper MOSFET off. When the output 

voltage decays below the overvoltage threshold, normal 

operation automatically resumes. Once the soft-start 

sequence has completed, undervoltage protection will latch 

the channel off if the output drops below 75% of its set point 

value. There is no overvoltage protection for Channel 2 in 

DDR application.
Adjustable overcurrent protection (OCP) monitors the 

voltage drop across the r

DS(ON)

 of the lower MOSFET. If 

more precise current-sensing is required, an external current 

sense resistor may be used. The OCP threshold can be 

adjusted by the resistor on OCSET pin and the current 

sensing gain can be adjusted by the resistor from ISEN pin 

to the phase node of the converter. Any overcurrent on the 

second channel will be reflected to the first channel. There is 

no OCP for the second channel.
In order to alleviate the interaction between the two channels 

caused by the switching noise, a phase shift has been 

implemented on the controller. If the input voltage is above 

5V, the VIN pin should connect the input voltage. This would 

provide the input voltage feed forward function and 

command the second channel 90 degree lagging the first 

channel. If the input voltage is at 3.3V, the VIN pin should 

connect to ground. This would result in a fixed ramp for the 

PWM comparator and command an in-phase operation of 

the two channels.

Features

• Provides regulated output voltage in the range of 0.9V–5.5V

- High efficiency over wide load range
- Synchronous buck converter with hysteretic operation at 

light load

- Selection of hysteretic/CCM mode on channel 1. Forced 

CCM on channel 2 for DDR application

• Uses MOSFET r

DS(ON) 

for current sensing or uses 

current-sense resistor for precision overcurrent protection

• Overvoltage, undervoltage and overcurrent protection

• Undervoltage lock-out on VCC pin

• Dual input voltage mode operation

- Operates directly from battery 5V to 24V input
- Operates from 3.3V or 5V system rail

• Excellent dynamic response

- Combined voltage feed-forward and current mode 

control

• Power-good signal for channel 1 in DDR application

Pinout

ISL6227 (28 LD SSOP) 

TOP VIEW

Ordering Information

PART #

TEMP. (°C)

PACKAGE

PKG 

DWG #

ISL6227CA

-10 to 100 28 Ld SSOP

M28.15

ISL6227CAZ
(Note)

-10 to 100 28 Ld SSOP (Lead-Free)

M28.15

ISL6227CA-T

-10 to 100 28 Ld SSOP Tape and Reel M28.15

ISL6227CAZ-T
(Note)

-10 to 100 28 Ld SSOP Tape and Reel 

(Lead-Free)

M28.15

NOTE: Intersil Lead-Free products employ special lead-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and lead-
free soldering operations. Intersil Lead-Free products are MSL
classified at lead-free peak reflow temperatures that meet or exceed
the lead-free requirements of IPC/JEDEC J Std-020B.

EN1

GND

DDR

VSEN1

VIN

PG1

VCC

VOUT1

ISEN1

LGATE1

PGND1

BOOT1

UGATE1

PHASE1

ISEN2

LGATE2
PGND2

BOOT2

UGATE2

PHASE2

EN2

VSEN2

VOUT2

OCSET2

OCSET1

SOFT1

SOFT2
PG2/REF

28
27
26
25
24
23
22
21
20
19
18
17
16
15

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5
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9

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1-888-INTERSIL or 321-724-7143

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Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright Intersil Americas Inc. 2004. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

Application Note

June 2004

AN1067

Содержание ISL6227EVAL1

Страница 1: ...from ISEN pin to the phase node of the converter Any overcurrent on the second channel will be reflected to the first channel There is no OCP for the second channel In order to alleviate the interacti...

Страница 2: ...p JP1 shunted An AmpMeter may be connected across these pins to measure IC and GATE Drive Current JP5 shunted toward VINPRG when Vin 5V for feed forward and program 90 degree out of phase PWM for CH1...

Страница 3: ...J3 FIGURE 2 WIRING CONNECTIONS FOR ISL6227EVAL1 see Quick Setup Connect the positive terminal of the electronic load and the positive terminal of the DVM to the VTT terminal J6 Connect the negative t...

Страница 4: ...VM to the VCC terminal J4 Connect the negative terminal of the DVM to the GND terminal J1 Do not apply power yet 1c Connect VIN power supply Set the adjustable 24VDC output voltage to zero volts Conne...

Страница 5: ...indictor from RED to GREEN And the PGOOD voltage on J11 should be 5V equal to the VCC voltage 5d Read the DVM connected to the VDDQ terminal J5 It should show a value between 2 450V 2 550V 5e Read the...

Страница 6: ...20 10 0K C12 220u 4V R13 NI U2 FDS6912A 1 2 3 4 5 6 7 8 C2 10u 25V X5R C4 68u 16V R16 680 J11 C16 4 7u 10V JP3 TP1 VTT R3 0 R8 17 8K R18 680 J4 TP4 PHASE 1 R14 10 0K C5 4 7u 10V J1 J2 J7 J14 JP2 1 2 3...

Страница 7: ...x2 RETENTIVE 2 54mm ST Berg FCI 69190 202 5 JP1 JP5 CONN JUMPER 2PIN SHUNT SPC02SYAN 2 D1 D2 DIODE SCHOTTKYBARR SMD SOT323 3P 30V 2A ON Semiconductor BAT54WT1 T 1 CR1 LED SMD 4P OTHER POLARIZEDRED GRN...

Страница 8: ...8 Application Note 1067...

Страница 9: ...9 Application Note 1067...

Страница 10: ...10 Application Note 1067...

Страница 11: ...ware and or specifications at any time without notice Accordingly the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding For information regarding...

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