Intersil ISL5585EVAL4, Руководство пользователя

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9
January 24, 2005
Dual-board A-A Jumper Settings
All jumper settings are described in Tables 11A and 11B. All
other jumpers should be removed.
TABLE 11A. MASTER BOARD JUMPER POSITIONS
JUMPER DESCRIPTION
JP4 Connects the receive output of the CODEC (U6) to
the RSLIC receive input VRX. Signal path is AC
coupled.
JP7 Selects the 5V or 3.3V chip-set Hybrid Gain of the
CODEC, AC coupled by C
1
.
JP13 Selects Rx Gain for 5V or 3.3V RSLIC/CODEC
chip-set.
JP15 Selects Tx Gain for 5V or 3.3V RSLIC/CODEC
chip-set.
JP10, POSN 2 Sets the CODEC master clock to 512kHz.
JP11 Enables the on board logic multiplexer.
JP12 Configures board as master.
SECONDARY POWER CABLE
MASTER
SLAVE
FIGURE 4. FULL CHANNEL A-A CONFIGURATION CONNECTORS AND JUMPERS
0 1 0 x 1 1
0 1 x 1 0 0
0
POWER
SUPPLIES
TABLE 11B. SLAVE BOARD JUMPER POSITIONS
JUMPER DESCRIPTION
JP4 Connects the receive output of the CODEC (U6) to
the RSLIC receive input VRX. Signal path is AC
coupled.
JP7 Selects the 5V or 3.3V chip-set Hybrid Gain of the
CODEC, AC coupled by C
1
.
JP13 Selects Rx Gain for 5V or 3.3V RSLIC/CODEC
chip-set.
JP15 Selects Tx Gain for 5V or 3.3V RSLIC/CODEC
chip-set.
JP11 Configures the on board logic multiplexer to
receive MCLK and frame sync signals from the
master.
Application Note 1168