Error Reporting and Handling
Intel® Server Boards SE7320SP2 and SE7525GP2
Revision
4.0
126
6. Error Reporting and Handling
The BIOS indicates the current testing phase during POST by writing a hex code to I/O location
80h. If errors are encountered, error messages or codes are either displayed to the video
screen, or if an error has occurred prior to video initialization, errors are reported through a
series of audio beep codes.
The error codes are defined by Intel and whenever possible are backward compatible with error
codes used on earlier platforms.
6.1 Error
Logging
This section defines how errors are handled by the system BIOS. Also discussed is the role of
the BIOS in error handling and the interaction between the BIOS, platform hardware, and server
management firmware with regard to error handling. In addition, error-logging techniques are
described and beep codes for errors are defined.
6.1.1
Error Sources and Types
One of the major requirements of server management is to correctly and consistently handle
system errors. System errors can be categorized as follows:
PCI bus
Memory multi-bit errors (single-bit errors are not logged)
Sensors
Processor internal errors, bus/address errors, thermal trip errors, temperatures and
voltages, and GTL voltage levels
Errors detected during POST, logged as POST errors
Sensors are managed by the mBMC. The mBMC is capable of receiving event messages from
individual sensors and logging system events.
6.1.2 SMI
Handler
The SMI handler handles and logs system-level events that are not visible to the server
management firmware. If SEL error logging is disabled in the BIOS Setup utility, no SMI signals
are generated on system errors. If error logging is enabled, the SMI handler preprocesses all
system errors, even those that are normally considered to generate an NMI.
The SMI handler sends a command to the BMC to log the event and provides the data to be
logged. For example, The BIOS programs the hardware to generate an SMI on a single-bit
memory error and logs the location of the failed DIMM in the system event log.
6.1.2.1
PCI Bus Error
The PCI bus defines two error pins, PERR# and SERR#, for reporting PCI parity errors and
system errors, respectively. The BIOS can be instructed to enable or disable reporting the
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