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Intel

PXA27x Processor Developer’s Kit - User’s Guide

3.5

General Purpose Input/Output (GPIO)

The interfaces between the main board and the Intel

PXA270 Processor take place through the

Intel

PXA270 Processor GPIO pins, as shown in

Table 33

For instructions on programming the GPIO pins, refer to the GPIO chapter in the

Intel

PXA27x

Processor Family Developer’s Manual

Note:

In the table, the direction shown is

relative to the processor

Table 33. GPIO Map (Sheet 1 of 4)

GPIO

Alternate Functions Direction Description

GPIO0

Platform interrupt source from FPGA

GPIO1

Platform interrupt source from main board switch SW21

SYS_EN

Power system enable

PWR_SCL

I/O

C power management clock

PWR_SDA

I/O

C power management data

PWR_CAP0

—

Sleep/deep-sleep regulator capacitor

PWR_CAP1

—

Sleep/deep-sleep regulator capacitor

PWR_CAP2

—

Sleep/deep-sleep regulator capacitor

PWR_CAP3

—

Sleep/deep-sleep regulator capacitor

CLK_PIO

I/O

Processor clock — direction depends on clock source (crystal,
oscillator, SMA, Baseband)

CLK_TOUT

32-kHz clock

SSPRXD2

SSP2 Receive

DD[7]

Camera Interface Data

SSPTXD2

SSP2 Transmit

L_VSYNC

Refresh sync signal from the LCD panel with internal frame buffer

nCS1

Static chip select for flash

PWM_OUT0

Pulse-width-modulated output — routed to LCD

PWM_OUT1 /
CIF_DD[6]

Pulse-width-modulated output / Camera Interface Data

RDY

Variable-latency I/O device ready for inserting wait states

L_CS

LCD chip select for panels with an internal frame buffer

MBREQ

Alternate Bus Mastering Request

MBGNT

Alternate Bus Mastering Grant

SSPSCLK2

I/O

SSP2 Clock

CIF_MCLK

Camera Interface Module Clock

CIF_FV

Camera Interface Frame Sync

CIF_LV

Camera Interface Line Sync

CIF_PCLK

Camera Interface Pixel Clock

CIF_DD[0]

Camera Interface Data

Содержание PXA27x Series

Страница 1: ...Intel PXA27x Processor Developer s Kit User s Guide April 2004 Revision 4 001 Order Number 278827 005 ...

Страница 2: ...fects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request This document and the software described in it are furnished under license and may only be used or copied in accordance with the terms of the license The information in this document is furnished for informational use only is subject to change w...

Страница 3: ... 2 9 PCMCIA 24 2 2 10 Audio Codecs 25 2 2 10 1 Philips UCB1400 25 2 2 11 Touch Screen Controllers 26 2 2 12 Keypad and Scroll Wheel Interface 26 2 2 13 MultiMediaCard Secure Digital Card 27 2 2 14 Memory Stick and Socket 27 2 2 15 USIM Connector 28 2 2 16 Camera Header 28 2 2 17 Bluetooth UART Radio Header 28 2 2 18 Baseband Header 28 2 2 19 Logic Analyzer Connectors 28 2 2 20 Silent Alert Motor C...

Страница 4: ...laneous Write Register 2 MSCWR2 59 3 2 2 7 Miscellaneous Write Register 3 MSCWR3 60 3 2 2 8 Miscellaneous Read Register 1 MSCRD1 61 3 2 2 9 Platform Interrupt Mask Enable Register INTMSKENA 63 3 2 2 10 Platform Interrupt Set Clear Register INTSETCLR 65 3 2 2 11 PCMCIA Socket 0 1 Status Control Registers PCMCIAx 67 3 2 2 12 FPGA Revision ID REVID 68 3 2 2 13 Scratch Registers1 2 3 SCRATCH1 2 3 69 3...

Страница 5: ...t Main Board 20 8 Intel PXA27x Processor Developer s Kit Reset Structure 22 9 PCMCIA Interface Structure 25 10 Keypad diagram 27 11 Block Diagram Intel PXA27x Processor Developer s Kit Daughter Card 37 12 Connectors Intel PXA27x Processor Developer s Kit Daughter Card 38 13 Intel PXA27x Processor Developer s Kit Interrupt Scheme A 79 14 Intel PXA27x Processor Developer s Kit Interrupt Scheme B 80 ...

Страница 6: ...finitions 59 24 MSCWR3 Bit Definitions 60 25 MSCRD Bit Definitions 61 26 INTMSKEN Bit Definitions High Bits 63 27 INTMSKEN Bit Definitions Low Bits 63 28 INTSETCLR Bit Definitions High Bits 65 29 INTSETCLR Bit Definitions Low Bits 65 30 PCMCIA0 1 Bit Definitions 67 31 FPGA Bit Definitions 68 32 Scratch Register Bit Definitions 69 33 GPIO Map 81 ...

Страница 7: ...nd video processing operations 1 1 System Overview The kit provides access to most of the Intel PXA270 Processor native input output I O functions The kit kit consists of Intel PXA27x Processor Developer s Kit Main Board main board which contains peripheral and expansion capability to aid in application software development Intel PXA27x Processor Developer s Kit Daughter Card daughter card which c...

Страница 8: ...es that became available after the publication of this User s Guide The kit contents include Chassis Fastap keypad camera QVGA display Main Board Daughter Card Intel PXA27x Processor Card PMIC LDO card Audio Module Intel JTAG Cable1 Basic accessory kit keyboard SD card 1 4 Related Documents Effective use of the kit frequently requires reference to the manufacturer s data sheet for a device Table 1...

Страница 9: ...im MAX1602 data sheet http www maxim ic com Open HCI Open Host Controller Specification for USB http www usb org Universal Serial Bus Specification http www usb org PCMCIA JEIDA PC Card Standard Volume 2 Electrical Specification http www pcmcia org Philips UCB1400 CODEC http www philipssemiconductor com Philips ISP1301 USB OTG transceiver http www philipssemiconductor com Standard Microsystems Eth...

Страница 10: ......

Страница 11: ...tensive input output I O capability and user interface aids Section 2 3 Intel PXA27x Processor Developer s Kit Daughter Card The daughter card contains the Intel PXA27x Processor Card processor card memory nominal I O capability and the required power circuitry Intel PXA27x Processor Developer s Kit Power Manager Integrated Circuit Low DropOut Card PMIC card for two modes of operation When docked ...

Страница 12: ... to the applications processor Note Most of the switches on the main board are SPDT slide switches with one of the positions identified by a DOT Switch positions are thus indicated as DOT or NO DOT The switches on the daughter card are DIP switches and are indicated as ON or OFF 2 1 User Interface Panel The user interface panel shown in Figure 1 contains the following items LCD Panel The liquid cr...

Страница 13: ...mera 2 2 Intel PXA27x Processor Developer s Kit Main Board The main board hosts a daughter card The daughter card hosts a processor card and a PMIC card The main board provides the expansion and I O functionality for a full featured development system The main board includes these features Transparent plastic cover and convenient layout for easy access to components Daughter card connectors 2 prog...

Страница 14: ...ctor Camera Interface Header Matrix keypad and scroll wheel connectors Silent Alert motor control header Logic analyzer connectors 8 discrete general purpose switches 8 discrete general purpose LEDs 2 hexadecimal encoded rotary switches 8 digit seven segment hex LED display Figure 2 shows the main board s organization in a block diagram Figure 3 through Figure 6 show the main board s layout and th...

Страница 15: ...V 2 5V FPGA CPLD core Main_3 15V Main_5V PCMCIA SIM 1 8 3V Wall Supply Jack Silent Alert Header PCMCIA_CONTROL PERIPHERAL_COMM Primary Connector IrDA Controlled by FPGA RS 232 M UART2 UART3 I2S I2C SSP I2S I2C SSP AC 97 I2S I2C SSP1 SSP2 SSP3 CPLD2 PCMCIA Glue PCMCIA xcvr control Memory Bus xcvr control UARTs mux Audio Board Logic 3 15V l 0 5V tolerant FPGA Flash Platform Registers PCMCIA power co...

Страница 16: ...ICC Audio CPLD2 EEPROM FPGA Primary Connector Buffers JTAG ICE RS232 XCVR CPLD1 JTAG Isolate Intel PXA27x Processor Intel PXA27x Processor Card CPLD1 Flash 32MB 32 SDRAM 64MB 32 SRAM 1MB 32 CPU JTAG Full Bandwidth MSL PCMCIA 3 0V I2C I2C Power 3 0V 12C V SRAM 1 8V I2S CODEC AC97 CODEC Line in out Line in out Linear CODEC V PLL 1 2V V Core 1 2V V IO 2 8V V SRAM 1 3V V PLL 1 1V V Core 8 1 3V V IO 3 ...

Страница 17: ...B Client connector and is located near the J13 USB On the Go OTG connector While the J13 connector is visible the J13 silkscreening is covered with components and may be difficult to locate Use Figure 4 to locate these connectors Figure 4 Connectors Intel PXA27x Processor Developer s Kit Main Board Top CPU ECO Sticker J11 J9 J18 J15 J25 J17 J20 J26 J40 J43 J21 J62 J61 J60 J23 J14 J8 J7 J6 J5 J2 J3...

Страница 18: ...18 Intel PXA27x Processor Developer s Kit User s Guide Figure 5 Connectors Intel PXA27x Processor Developer s Kit Main Board Bottom J48 J49 J50 J51 J53 J52 ...

Страница 19: ...x Processor Developer s Kit User s Guide 19 Figure 6 Switches Intel PXA27x Processor Developer s Kit Main Board SW22 SW21 SW20 SW19 SW18 SW17 SW16 SW15 SW14 SW13 SW12 SW11 SW10 SW9 SW8 SW7 SW6 SW5 SW1 SW3 SW2 SW4 ...

Страница 20: ...ntel PXA27x Processor Developer s Kit User s Guide Figure 7 LEDs Intel PXA27x Processor Developer s Kit Main Board D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D20 D22 D23 D15 D14 D18 D17 D13 D16 D19 D21 D24 D25 ...

Страница 21: ...m registers and flash memory bank 2 Voltage supervisor U18 monitors the Intel PXA270 Processor s VCC RTC supply as it ramps up This supply from the PMIC card is always enabled regardless of any low power state of the processor 3 A minimum of 140 ms after the VCC RTC supply has stabilized the open drain supervisor outputs release nTRST and nRESET thus deasserting nTRST through a pull up resistor Th...

Страница 22: ...it Reset Structure B1728 01 Intel PXA27x Processor DVK nRESET nRESET_OUT CPLD1 Flash Flash JTAG ICE nTRST Daughter Card Main Board RS 232 XCVR nReset nRST nRST FPGA_DONE nSYS_RST CPLD2 Ethernet Controller Flash Bank Expansion SV FPG Controller DONE nPROGRAM nFPGA_RST nDRCD_PRES Comm Reset Switch Intel PXA27x Reset Switch nRESET nRESET_OUT COMMS_SW_RESET FPGA Board Registers nCS2L Switch SW9 Commun...

Страница 23: ...tion Register SCR on page 51 The default bus width for both the main board and processor card s flash memory banks is 32 bits The main board flash memory bank but not the Synchronous Intel StrataFlash Wireless memory L18 processor card flash memory bank can optionally be set to operate on a 16 bit bus If it is necessary to boot using a 16 bit bus two switches must be changed as follows 1 Set main ...

Страница 24: ...e expansion The Intel PXA270 Processor supports software control of the connection state of the USB client through a bit in Miscellaneous Write Register 2 See section Section 3 2 2 6 Miscellaneous Write Register 2 MSCWR2 on page 59 for more information For details of the external USB interface see the Universal Serial Bus Specification Revision 1 1 and the Open HCI Open Host Controller Specificati...

Страница 25: ...may be inserted The current available options for this connector are an AC 97 codec the Philips UCB1400 2 2 10 1 Philips UCB1400 The Philips UCB1400 codec supports 20 bit stereo audio with programmable sampling rate input and output gain control and digital sound processing The UCB1400 provides the following features in addition to the codec Touch screen controller Figure 9 PCMCIA Interface Struct...

Страница 26: ...0 codec board touch screen controllers UCB1400 The default touch screen controller contained in the Philips UCB1400 communicates with the Intel PXA270 Processor through the AC97 controller This is a four wire resistive controller supporting position pressure and plate resistance measurements 2 2 12 Keypad and Scroll Wheel Interface The panel mounted Fastap keypad and scroll wheel use the Intel PXA...

Страница 27: ...ure Digital I O controller The main board socket supports both types of cards This controller is multiplexed with the Memory Stick controller so only one SD MMC or Memory Stick may be used at a time 2 2 14 Memory Stick and Socket The Sony Memory Stick socket connects to the Intel PXA270 Processor Memory Stick controller It is multiplexed with the SD SDIO MMC controller so only one may be used at a...

Страница 28: ...tely 2 2 17 Bluetooth UART Radio Header The Intel PXA270 Processor Bluetooth UART appears on two main board connectors a radio header for interfacing with UART based radio cards a DB 9 connector for debugging use SW6 Auxiliary UART Bluetooth Header DOT BTUART Reserved NO DOT Reserved BTUART 2 2 18 Baseband Header The baseband header runs at 3 15 volts nominally and interfaces with the Intel MSL mo...

Страница 29: ... are defined as follows DD1 Link software defined DD2 Transmit Receive software defined DD3 General purpose software defined 2 2 23 Fault Emulation Switches The nBATT_FLT and nVDD_FLT switches control the states of the Intel PXA270 Processor nBATT_FAULT and nVDD_FAULT pins These switches simulate the error conditions that is they functionally work the same and are used to signal the Intel PXA270 P...

Страница 30: ... see the kit main board schematic diagram To identify a connector s type see the main board parts list Table 2 Connectors Intel PXA27x Processor Developer s Kit Main Board Sheet 1 of 3 Designator Name J1 USB client J2 Ethernet J3 USB host 1 reserved J4 USB host 0 J5 Line2 Output J6 Line2 Input J7 Line1 Speaker Headphone J8 Line1 Input J9 Compatible Audio connector J10 Alternate speaker connector J...

Страница 31: ...emory Stick Socket J45 Bluetooth GPS Radio Header J46 Graphics Accelerator Test Clock SMA Connector J47 DB 9 RS232 Header J48 Line1 Mic Headset Jack J49 Alternate Microphone Connector J50 PCMCIA Card Cage J51 PCMCIA Socket J52 Audio CODEC Connector J53 SD SDIO MMC Socket J54 Test header J54 1 3 5 GND J54 2 HFK_LINE_OUT J54 4 HFK_MIC_IN J55 Right audio channel amplifier select J56 BlueTooth power s...

Страница 32: ...faces Table 2 Connectors Intel PXA27x Processor Developer s Kit Main Board Sheet 3 of 3 Designator Name Table 3 Switches and Settings Intel PXA27x Processor Developer s Kit Main Board Sheet 1 of 2 Switch Name Function SW1 SW2 SW3 LAN91C111 IOS0 LAN91C111 IOS1 LAN91C111 IOS2 Ethernet controller chip mode control pins DOT open pin pulled high internally NO DOT pin low SW4 LAN91C11 IOS3 Enable disabl...

Страница 33: ...9 SW20 SW21 GPSWT3 GPSWT4 GPSWT5 GPSWT6 GPSWT7 General purpose discrete switches DOT user defined NO DOT user defined SW22 Power switch Center OFF power inputs floating Right OFF power inputs shorted to ground Left ON Caution Do not change this switch setting while power is on Table 3 Switches and Settings Intel PXA27x Processor Developer s Kit Main Board Sheet 2 of 2 Switch Name Function Table 4 ...

Страница 34: ...power indicator Red D16 1 8V power indicator Red D17 SD PWR SD MMC power indicator Red D18 MS PWR Memory Stick Power Indicator Red D19 3 15V power indicator Red D20 Discrete LED 5 General purpose user writable Green D21 12V power indicator Red D22 23 Discrete LED 6 7 General purpose user writable Green D24 2 5V power indicator Red D25 5V power indicator Red Table 4 LED Indicators Intel PXA27x Proc...

Страница 35: ..._SIM 3 Red PCMCIAV_0 20 Red DC_2P5V 4 Black GND 21 Red DC_3P15V 5 Yellow NPCMCIA0_OE 22 Black GND 6 Red PCMCIAV_1 23 Black GND 7 Yellow PCMCIA_DIR 24 Black GND 8 Yellow NPCMCIA1_OE 25 Yellow USIM_DET 9 Black GND 26 Red MMC_3P15V 10 Yellow nPCMCIA0_DOE 27 Black GND 11 Yellow nPCMCIA1_DOE 28 Red MS_3P15V 12 Yellow DATA2_DIR 29 Red DC_1P8V 13 Yellow nDATA2_OE 30 Yellow MSINS 14 Black GND 31 Red DC_12...

Страница 36: ...2 shows the connectors switches and LEDs When docked with the main board the daughter card becomes a full featured evaluation system The daughter card memory and off chip components operate from the 1 8 volt power supply which provides the best power efficiency The daughter card includes the following features 2 Mbytes SRAM User interface via a full featured serial port JTAG in circuit emulation I...

Страница 37: ... OTG Keypad UICC Audio CPLD2 EEPROM FPGA Primary Connector Buffers JTAG ICE RS232 XCVR CPLD1 JTAG Isolate Intel PXA27x Processor Intel PXA27x Processor Card CPLD1 Flash 32MB 32 SDRAM 64MB 32 SRAM 1MB 32 CPU JTAG Full Bandwidth MSL PCMCIA 3 0V I2C I2C Power 3 0V 12C V SRAM 1 8V I2S CODEC AC97 CODEC Line in out Line in out Linear CODEC V PLL 1 2V V Core 1 2V V IO 2 8V V SRAM 1 3V V PLL 1 1V V Core 8...

Страница 38: ... Daughter Card Intel PXA27x Processor Card J26 J25 J30 on bottom of card J29 on bottom of card J21 J20 J22 J27 J19 SW2 J15 J16 J17 J18 J9 SW1 J5 J3 J32 J4 J2 Intel PXA27x Processor Developer s Kit PMIC LDO Card J36 J31 J38 J14 J6 J33 J1 J34 J23 J24 J35 J39 J11 J7 Intel PXA27x Processor Developer s Kit Daughter Card ...

Страница 39: ...4 Stand Alone I O Interface When the daughter card operates in stand alone mode the RS 232 serial port see Section 2 3 5 provides the interface to a host computer or other serial device at speeds up to 115 kbps The JTAG interface see Section 2 3 6 provides debugging and software downloading 2 3 5 Full Featured RS 232 Serial Port The Intel PXA270 Processor Full Featured UART controller connects to ...

Страница 40: ... necessary configuration information For details of the System Configuration Register see Section 3 2 1 Virtual Configuration Registers on page 50 2 3 9 Connectors Table 7 lists all of the connectors on the daughter card For the locations of connectors on the daughter card see Figure 12 For descriptions of a connector s use see the referenced section in this document For pin assignments see the da...

Страница 41: ...rd Primary Connector J54 Test header J54 1 3 5 GND J54 2 HFK_LINE_OUT J54 4 HFK_MIC_IN J55 and J58 Right audio channel amplifier select J57 and 59 left audio channel amplifier select J56 BlueTooth power select J56 1 VCCP_3V J56 3 DC_3P15V J60 audio card power select 1 8V J60 1 DC_1P8V J60 3 D2_1V8 J61 audio card power select 3V J61 1 AUDIO_4P5V J61 3 VCCP_3V J62 audio card power select 3 15V J62 1...

Страница 42: ...cators on the daughter card See Figure 6 for their locations Table 9 Switches and Settings Daughter Card Switch Function SW1 1 JTAG Chain Select ON SW2 setting determines the JTAG Chain configuration OFF JTAG Chain is connected to CPLD1 SW1 2 Reserved SW1 3 Intel MSL Routing OFF Intel MSL routed to main board Baseband header SW1 4 Reserved Always connect to OFF SW1 5 Reserved SW1 6 Processor Bus B...

Страница 43: ...onous flash memory normally serve as the system s boot ROM mapped to Intel PXA270 Processor Chip Select nCS0 A switch on the main board allows swapping an nCS0 signal to the flash memory bank on the main board which then serves as the boot ROM For more information on using the Flash memory as the boot source see Section 2 2 3 Note The processor card s L18 flash memory always uses a 32 bit bus Do n...

Страница 44: ...hereafter if not changed by the PWR_I2C bus the control voltage applied to the regulator defaults to 0 which produces a DC_CORE voltage of 1 417 volts Note Carefully observe the PWR_I2C programming instructions in the Intel PXA27x Processor Family Developer s Manual It is possible to set the output from the regulator to a voltage at which the Intel PXA270 Processor cannot function less than approx...

Страница 45: ... 045 275 1 339 800 1 030 300 1 323 825 1 016 325 1 309 850 1 001 350 1 294 875 0 986 375 1 280 900 0 972 400 1 265 925 0 957 425 1 251 950 0 942 450 1 236 975 0 928 475 1 221 1000 0 913 500 1 207 1023 0 899 Table 12 Programmable DC_CORE Voltages Sheet 2 of 2 Binary Input to DAC expressed in decimal DC_CORE Voltage Binary Input to DAC expressed in decimal DC_CORE Voltage ...

Страница 46: ...l PXA27x Processor Developer s Kit User s Guide 2 5 2 PMIC Card Jumper Settings The diagram below illustrates the jumper settings of the PMIC card The diagram also illustrates the functionality of the jumpers ...

Страница 47: ... Board Support Package for the exact values used 3 1 Memory Map and Chip Selects Table 13 describes the physical addresses and active low chip selects for the Intel PXA27x Processor Card processor card For a complete listing of the Intel PXA270 Processor memory map refer to the Memory Controller chapter in the Intel PXA27x Processor Family Developer s Manual Note There is no difference in the memo...

Страница 48: ...0x5800_0000 0x5BFF_FFFF Internal memory storage 64 Mbytes 0x5C00_0000 0x5FFF_FFFF reserved 256 Mbytes 0x6000_0000 0x6FFF_FFFF reserved 256 Mbytes 0x7000_0000 0x7FFF_FFFF reserved 256 Mbytes 0x8000_0000 0x8FFF_FFFF reserved 256 Mbytes 0x9000_0000 0x9FFF_FFFF SDRAM bank 0 nSDCS0 64 Mbytes 0xA000_0000 0xA3FF_FFFF SDRAM bank 1 nSDCS1 64 Mbytes 0xA400_0000 0xA7FF_FFFF SDRAM bank 2 nSDCS2 64 Mbytes 0xA8...

Страница 49: ...ction 3 2 1 2 System Configuration Register 2 SCR2 Virtual Section 3 2 2 1 Hex LED Data Register 1 LEDDAT1 Memory mapped Section 3 2 2 2 Hex LED Data Register 2 LEDDAT2 Memory mapped Section 3 2 2 3 LED Control Register LEDCTRL Memory mapped Section 3 2 2 4 General Purpose Switch Register GPSWR Memory mapped Section 3 2 2 5 Miscellaneous Write Register 1 MSCWR1 Memory mapped Section 3 2 2 6 Miscel...

Страница 50: ...these steps Caution Before performing this routine ensure that the LCD interface is idle 1 Configure all GPIO pins excluding the virtual data pins listed in Table 15 that are to be read to their correct alternate functions and initial logic levels shown in Table 33 2 Enable the GPIO pin inputs by clearing the read disable hold RDH bit in the Intel PXA270 Processor Power Manager Sleep Status Regist...

Страница 51: ...ion 15 SWAP_ FLASH R Status of main board switch SW2 0 DOT position nCS0 connects to Intel PXA270 Processor flash memory nCS1 to main board flash memory The system boots from the Intel PXA270 Processor bank 1 NO DOT position nCS0 connects to main board flash memory nCS1 to Intel PXA270 Processor flash memory The system boots from the main board bank 14 13 EXBID R expansion board ID reserved 12 nEX...

Страница 52: ...System configuration word SCR2 Intel PXA27x Processor Developer s Kit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO 103 104 113 31 30 87 86 77 75 74 19 14 Name Reserved nGFX_PRES AUDIOID ORIENT LCDID Reset Bits Name Access Description 15 11 reserved 10 nGFX_PRES R Graphics Accelerator Present 0 Graphics Accelerator is present 1 Graphics Accelerator is absent 9 7 AUDIOID Audio CODEC ID 0b000 Reser...

Страница 53: ...ation about the hex LED displays see Figure 3 on page 16 and Table 4 on page 33 To control the decimal points and dots see Section 3 2 2 2 To blank the digits see Section 3 2 2 3 Table 18 LEDDAT1 Bit Definitions Physical Addresses 0x0800_0010 LEDDAT1 Intel PXA27x Processor Developer s Kit Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name DIGIT7 DIGIT6 D...

Страница 54: ...nore reads from reserved bits Write 0b0 to reserved bits Table 19 LEDDAT2 Bit Definitions Physical Address 0x0800_0014 LEDDAT2 Intel PXA27x Processor Developer s Kit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name DIGIT7DP DIGIT6DP DIGIT5DP DIGIT4DP DIGIT3DP DIGIT2DP DIGIT1DP DIGIT0DP reserved HEX1L3 HEX1L2 HEX1L1 HEX0L3 HEX0L2 HEX0L1 Reset 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 Bits Name Access Descripti...

Страница 55: ...per s Kit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name BLANK7 BLANK6 BLANK5 BLANK4 BLANK3 BLANK2 BLANK1 BLANK0 LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0 Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bits Name Access Description 15 8 BLANKx R W Blank the seven segment hex LED digits 0 digit ON 1 digit OFF BLANK7 HEX1 digit 1 U76 most significant digit BLANK6 HEX1 digit 2 U76 BLANK5 HEX1 digit 3 U76 BLANK4 ...

Страница 56: ...are on the kit They may be used as desired Table 21 GPSWR Bit Definitions Physical Address 0x0800_0060 GPSWR Intel PXA27x Processor Developer s Kit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name GPSWT7 GPSWT6 GPSWT5 GPSWT4 GPSWT3 GPSWT2 GPSWT1 GPSWT0 HEXSWT1 HEXSWT0 Reset Bits Name Access Description 15 8 GPSWTx R General purpose switch position 0 DOT 1 NO DOT GPSWT7 SW21 GPSWT6 SW20 GPSWT5 SW19 G...

Страница 57: ...rol 0 Signals are routed to SSP1 USIM and PWM1 1 Signals are routed to the Camera Interface 13 LCD_CTL R W General purpose LCD control signal use varies with the LCD module being used 12 MS_ON R W Memory Stick power control 0 power off 1 power on 11 MMC_ON R W MultiMediaCard power control 0 power off 1 power on 10 MS_SEL R W SD Memory Stick multiplexer control 0 Signals are routed to the SD MMC so...

Страница 58: ...W System reset 0 reset deasserted 1 reset asserted Table 22 MSCWR1 Bit Definitions Sheet 2 of 2 Physical Address 0x0800_0080 MSCWR1 Intel PXA27x Processor Developer s Kit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name CAMERA_ON CAMERA_SEL LCD_CTL MS_ON MMC_ON MS_SEL BB_SEL nBT_OFF BTDTR IrDA_MD IRDA_FIR GREENLED reserved MTR_ON SYSRESET Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Bits Name Access Descript...

Страница 59: ...7 L_DD17 0 Legacy mode nPCE1 GPIO85 BB_IB_WAIT nPCE2 GPIO54 BB_OB_WAIT 7 GRAPHICS_SEL R W Graphics Accelerator control 1 Graphics Accelerator enablednCS1 Graphics Accelerator nCS5 Graphics Accelerator 0 Graphics Accelerator disablednCS1 Secondary Flash nCS5 Expansion Board 6 USB_OTG_RST R W USB On The Go External Transceiver Reset 0 Hold USB OTG External transceivers in reset 1 Enable USB OTG Exte...

Страница 60: ...sor Developer s Kit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Reserved GPIO_RESET_EN GPIO_RESET COMMS_SW_RESET Reset 0 0 0 Bits Name Access Description 15 3 Reserved R W Reserved 2 GPIO_RESET_ EN R W Enable GPIO Resets 0 GPIO1 follows SW21 1 Enable GPIO Reset from Software or from SW21 1 GPIO_RESET R W Initiate a GPIO Reset 0 normal operation 1 Initiate GPIO reset 0 COMMS_SW_ RESET R W Commun...

Страница 61: ...essor Card 10 POLL_FLAG R Graphics Accelerator Poll Flag signal 0 Graphics Accelerator Poll Flag is low 1 Graphics Accelerator Poll Flag is high 9 nPENIRQ R ADI7873 touch screen digitizer nPENIRQ signal 0 nPENIRQ is low 1 nPENIRQ is high 8 nMEMSTK_ CD R Memory Stick detection signal 0 Card is fully inserted 1 Card is not fully inserted or is not present 7 nMMC_CD R SD MMC card detection signal 0 C...

Страница 62: ...s not write protected Reset values depend on the states of the corresponding signals Table 25 MSCRD Bit Definitions Sheet 2 of 2 Physical Address 0x0800_0090 MSCRD Intel PXA27x Processor Developer s Kit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name reserved nFPG_PRES POLL_FLAG nPENIRQ nMEMSTK_CD nMMC_CD nUSIM_CD USB_CBL TS_BUSY BTDSR BTRI BTDCD nMMC_WP Reset Bits Name Access Description ...

Страница 63: ...INT PMC_IRQ Reset 0 0 0 0 Bits Name Access Description 31 20 reserved R W reserved 19 INT_Mx R W Graphics Accelerator Interrupt Request 18 BT_RI_INT R W Bluetooth Ring Indicator Interrupt Request 17 BT_DTR_INT R W Bluetooth UART Data Terminal Ready Interrupt Request 16 PMC_IRQ R W Power Management IC Interrupt Request Table 27 INTMSKEN Bit Definitions Low Bits Sheet 1 of 2 Physical Address 0x0800_...

Страница 64: ...ntroller IRQ 2 USBC R W USB client cable detection IRQ 1 USIM R W USIM card detection IRQ 0 MMC R W MMC SD card detection IRQ Table 27 INTMSKEN Bit Definitions Low Bits Sheet 2 of 2 Physical Address 0x0800_00C0 INTMSKEN Intel PXA27x Processor Developer s Kit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name S1_IRQ S1_STSCHG S1_CD reserved S0_IRQ S0_STSCHG S0_CD reserved nEXBRD_INT MSINS PENIRQ AC97 E...

Страница 65: ..._INT BT_DTR_INT PMC_IRQ Reset 0 0 0 0 Bits Name Access Description 31 20 reserved R W reserved 19 INT_Mx R W Graphics Accelerator Interrupt Request 18 BT_RI_INT R W Bluetooth Ring Indicator Interrupt Request 17 BT_DTR_INT R W Bluetooth UART Data Terminal Ready Interrupt Request 16 PMC_IRQ R W Power Management IC Interrupt Request Table 29 INTSETCLR Bit Definitions Low Bits Sheet 1 of 2 Physical Ad...

Страница 66: ...ET R W Ethernet controller IRQ 2 USBC R W USB client cable detection IRQ 1 USIM R W USIM card detection IRQ 0 MMC R W MMC SD card detection IRQ Table 29 INTSETCLR Bit Definitions Low Bits Sheet 2 of 2 Physical Address 0x0800_00D0 INTSETCLR Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name S1_IRQ S1_STSCHG S1_CD reserved S0_IRQ S0_STSCHG S0_CD reserved nEXBRD_INT MSINS PENIRQ AC97 ETHERNET USBC USIM M...

Страница 67: ...gram for implementation details Note Ignore reads from reserved bits Write 0b0 to reserved bits Attempted writes to read only bits are ignored Table 30 PCMCIA0 1 Bit Definitions Sheet 1 of 2 Physical Address 0x0800_00E0 0x0800_00E4 PCMCIA0 x socket 0 PCMCIA1 x socket 1 Intel PXA27x Processor Developer s Kit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name reserved Sx_nIRQ Sx_nSPKR_ BVD2 Sx_nSTSCHG_ ...

Страница 68: ...ates of the corresponding signals Table 30 PCMCIA0 1 Bit Definitions Sheet 2 of 2 Physical Address 0x0800_00E0 0x0800_00E4 PCMCIA0 x socket 0 PCMCIA1 x socket 1 Intel PXA27x Processor Developer s Kit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name reserved Sx_nIRQ Sx_nSPKR_ BVD2 Sx_nSTSCHG_ BVD1 Sx_nVS Sx_nCD Sx_RESET Sx_PWR Reset 1 0 0 0 0 Bits Name Access Description Table 31 FPGA Bit Definitions...

Страница 69: ... memory control registers These settings are required for proper operation of the Intel PXA270 Processor in a stand alone application or in combination with the main board The following registers must be configured Section 3 3 1 1 SDRAM Configuration Register MDCNFG Section 3 3 1 2 SDRAM Mode Register Set Configuration Register MDMRS Section 3 3 1 3 SLP SDRAM Mode Register Set Configuration Regist...

Страница 70: ...egister Set Configuration register see the Memory Controller chapter in the Intel PXA27x Processor Family Developer s Manual It may be necessary to adjust the recommended settings depending on the following Desired clock sources for example core PLL instead of internal or external processor oscillator See the Clocks and Power Manager chapter in the Intel PXA27x Processor Family Developer s Manual ...

Страница 71: ...A270 Processor with main board 000 X X X XX X XX XX X XX 000 0 1 0 10 1 10 01 0 00 See SDRAM Initialization Memory Controller chapter Intel PXA27x Processor Family Developer s Manual 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Stand alone Intel PXA270 Processor and Intel PXA270 Processorwith main board 0 XXXX XXXX 000 0 000 0 0000 0000 000 0 000 Burst read...

Страница 72: ...0 0 12 X 0 13 1 1 X4 1 0 0000 0001 11105 NOTES 1 SDCLK0 MEMCLK 4 2 Auto power down APD enabled for all devices except synchronous flash memory devices To identify the types used in the kit system see Section 2 2 3 Flash Memory and Boot ROM on page 23 and Section 2 4 2 Flash Memory on page 43 See also the kit parts lists For more information on the APD function see the MDREFR register description i...

Страница 73: ...1 0 010 1 010 0111 1010 0 011 Notes 1 3 1 3 1 3 1 3 1 2 3 1 3 1 4 5 1 4 5 1 4 5 1 4 5 1 4 5 1 4 5 NOTES 1 These values are based upon the main board switch SW2 SWAP_FLASH being set to DOT nCS0 Intel PXA270 Processor flash If SWAP_FLASH is set to NO DOT nCS0 main board flash then the upper and lower halves of this register must be swapped To determine the state of SWAP_FLASH software must use the p...

Страница 74: ...XXXX X XXX 1 100 1100 1101 0 001 On the kit the GPIO for nCS3 serves as the PCMCIA PSKTSEL signal Thus no memory is attached to nCS3 B 8 8 4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Stand alone Intel PXA270 Processor X1 XXX1 XXXX1 XXXX1 X1 XXX1 X XXX XXXX XXXX X XXX Processor card with main board X1 XXX1 XXXX1 XXXX1 X1 XXX1 1 0011 1000 10002 0 100 NOTES...

Страница 75: ...CATT0 MCATT1 MCIO0 and MCIO1 Recommended Settings 4 0 0 4 4 0 0 4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Stand alone Intel PXA270 Processor and Intel PXA270 Processor with main board 0 1 00 000 0000 001 00 0 1 00 000 0000 001 00 These values are based upon the main board switch SW2 SWAP_FLASH being set to DOT nCS0 Intel PXA270 Processor flash If SWAP_...

Страница 76: ...me the following Core is clocked off of the core PLL with a core run mode frequency of 130 MHz L 10 in the Core Clock Configuration Register The LCD controller frequency is 65 MHz see the Clocks and Power Manager chapter in the Intel PXA27x Processor Family Developer s Manual It may be necessary to adjust the recommended settings depending on the following Custom clock configurations Clock sources...

Страница 77: ...10 0111 1111 Toshiba LTM035A776C QVGA 0000 0100 0000 0100 0001 00 00 1110 1111 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Toshiba LTM04C380K VGA 0000 0000 0010 1101 00 0000 01 1101 1111 Toshiba LTM035A776C QVGA 0000 0011 0000 0011 0000 10 01 0011 1111 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Toshiba LTM04C380K ...

Страница 78: ...e table appear on the Intel PXA270 Processor general purpose I O pin GPIO0 as a composite active low signal General purpose main board switch SW21 maps through the main board FPGA to both the General Purpose Switch Register see Section 3 2 2 4 and to GPIO pin 1 SW12 may thus serve as an interrupt source When an interrupt occurs its bit gets set in the Interrupt Set Clear register Section 3 2 2 10 ...

Страница 79: ...ster Section 3 2 2 9 Platform Interrupt Mask Enable Register INTMSKENA on page 63 To enable the interrupt set its bit For more information about the peripherals and their interrupts refer to the manufacturer s data sheet Figure 13 Intel PXA27x Processor Developer s Kit Interrupt Scheme A A9891 01 GPIO0 Other Interrupts reglntSetClr X 1 regXXXSetClr GPIO1 AnyClr Switch SW12 Data X nWE_Rise nFpgaRst...

Страница 80: ...7x Processor Developer s Kit User s Guide Figure 14 Intel PXA27x Processor Developer s Kit Interrupt Scheme B A9905 01 nGPIO 0 Other Interrupts reglntSetClr X AnyClr Data X nWE_Rise nFpgaRst Q D CLK CLR XXX_Int PRE ...

Страница 81: ...lator capacitor 7 PWR_CAP2 Sleep deep sleep regulator capacitor 8 PWR_CAP3 Sleep deep sleep regulator capacitor 9 CLK_PIO I O Processor clock direction depends on clock source crystal oscillator SMA Baseband 10 CLK_TOUT O 32 kHz clock 11 SSPRXD2 I SSP2 Receive 12 DD 7 I Camera Interface Data 13 SSPTXD2 O SSP2 Transmit 14 L_VSYNC I Refresh sync signal from the LCD panel with internal frame buffer 1...

Страница 82: ...al ready SSPRXD2 direction depends on usage USB OTG 41 FFRTS O FFUART request to send 42 BTRXD I Bluetooth UART serial data input 43 BTTXD O Bluetooth UART serial data output 44 BTCTS I Bluetooth UART clear to send 45 BTRTS O Bluetooth UART request to send 46 ICP_RXD I Infrared serial data input 47 ICP_TXD O Infrared serial data output 48 BB_OB_DAT1 O Baseband outbound data bits 49 nPWE O PCMCIA c...

Страница 83: ...a line and SCR bit direction depends on usage 71 L_DD13 I O LCD data line and SCR bit direction depends on usage 72 L_DD14 I O LCD data line and SCR bit direction depends on usage 73 L_DD15 I O LCD data line and SCR bit direction depends on usage 74 L_FCLK O LCD frame Clock 75 L_LCLK O LCD line Clock 76 L_PCLK O LCD pixel Clock 77 L_BIAS O LCD Bias 78 nCS2 O Static chip select for FPGA CPLD2 79 PS...

Страница 84: ...KOUT0 O Matrix keypad output 104 KP_MKOUT1 O Matrix keypad output 105 KP_MKOUT2 O Matrix keypad output 106 KP_MKOUT3 O Matrix keypad output 107 KP_MKOUT4 O Matrix keypad output 108 KP_MKOUT5 O Matrix keypad output 109 MMDAT1 MSSDIO I O MMC data line Memory Stick data signal 110 MMDAT2 I O MMC data line 111 MMDAT3 I O MMC data line 112 MMCMD MSINS I O MMC bidirectional line for command Memory Stick...

Страница 85: ...f two cables and an interface module To install thethis hardware and prepare the kit for programming follow these steps 1 Turn off the kit power 2 Attach the 25 pin parallel port cable between the host computer s parallel port and the matching connector on the interface card 3 Attach the 20 pin ribbon cable between the matching connector on the interface card and the JTAG connector J3 on the Intel...

Страница 86: ...LD code For example the file for the Intel PXA270 Processor is ms2_drcd_cpld_1_00 jed To program CPLD1 follow these steps 1 Complete the setup instructions set out in Section 3 6 0 1 and its subsections 2 Set daughter card switch SW1 1 to the OFF position CPLD1 attached to the to JTAG chain 3 Apply power to the kit 4 Start the Xilinx programming software 5 Follow the instructions in the Xilinx sof...

Страница 87: ...s on using the XPLA programming software see the Xilinx web site After programming is complete return the kit to normal operation as follows 1 Exit the XPLA programming software 2 Turn off power to the kit 3 Return SW2 1 and SW2 2 to the default ON position Caution Disconnect the JTAG cable from the Intel PXA270 Processor to avoid damage to the kit 3 6 4 FPGA Configuration EEPROM Main Board U15 on...

Страница 88: ...ACT programming software and install it on the host computer 5 Start the iMPACT software and use it to reprogram CPLD2 When prompted for a design file use the JEDEC file obtained above For instructions on using the XPLA programming software see the Xilinx web site After programming is complete return the kit to normal operation as follows 1 Exit the XPLA programming software 2 Turn off power to th...

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