87
Technical Product Specification
Specifications
A.6.6
H.110 P4/P5 Interface
This section defines the P4/P5 interface for H.110 slots.
specifies the P4 interface for the H.110 slots. This is in accordance with the PICMG* 2.5
R1.0 specification. Refer to the PICMG specification for more detail.
The P5 interface for the H.110 slots is defined in the PICMG* 2.5 R1.0 specification. There are no
deviations from the specification for this interface.
Table 30. H.110 P4 Pin Assignments
Pin #
A
B
C
D
E
F
25
SGA4
SGA3
SGA2
SGA1
SGA0
FGND
24
GA4
GA3
GA2
GA1
GA0
FGND
23
+12V
/CT_Reset
/CT_EN
-12V
CT_MC
FGND
22
PFS0#
RSVD
RSVD
RSVD
RSVD
FGND
21
-SEL Vbat
1
PFS1#
RSVD
RSVD
-SEL Vbat Rtn
1
FGND
20
[No Pin]
[No Pin]
[No Pin]
[No Pin]
[No Pin]
[No Pin]
19
[No Pin]
[No Pin]
[No Pin]
[No Pin]
[No Pin]
[No Pin]
18
VRG
2
[No Pin]
[No Pin]
[No Pin]
VRG Rtn
2
[No Pin]
17
[No Pin]
[No Pin]
[No Pin]
[No Pin]
[No Pin]
[No Pin]
16
[No Pin]
[No Pin]
[No Pin]
[No Pin]
[No Pin]
[No Pin]
15
-Vbat
2
[No Pin]
[No Pin]
[No Pin]
-Vbat Rtn
2
[No Pin]
14
(KEY)
13
12
11
CT_D29
CT_D30
CT_D31
V(I/O)
/CT_FRAME_A
GND
10
CT_D27
3.3V
CT_D28
5V
/CT_FRAME_B
GND
9
CT_D24
CT_D25
CT_D26
GND
/FR_COMP
GND
8
CT_D21
CT_D22
CT_D23
5V
CT_C8_A
GND
7
CT_D19
5V
CT_D20
GND
CT_C8_B
GND
6
CT_D16
CT_D17
CT_D18
GND
CT_NETREF_1
GND
5
CT_D13
CT_D14
CT_D15
3.3V
CT_NETREF_2
GND
4
CT_D11
5V
CT_D12
3.3V
SCLK
GND
3
CT_D8
CT_D9
CT_D10
GND
SCLKx2
GND
2
CT_D4
CT_D5
CT_D6
CT_D7
GND
GND
1
CT_D0
3.3V
CT_D1
CT_D2
CT_D3
GND
NOTES:
1. The –SEL Vbat and –SEL Vbat Rtn signals are routed to support Safety Extra Low Voltage (SELV) on the
midplane. The ZT 5085 does not provide the SEL Vbat power source.
2. The VRG, VRG Rtn, -Vbat, and –Vbat Rtn signals are routed to support Secondary Hazardous (S-Haz)
voltages on the midplane. The ZT 5085 does not provide the VRG or Vbat power sources.
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