Intel NetStructure ZT 5085, Руководство пользователя

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Technical Product Specification
Specifications
Table 19. Slot P1 Pin Assignments
Pin # Z A B C D E F
25 GND 5 REQ64# ENUM# 3.3 V 5 V GND
24 GND AD[1] 5 V V(I/O) AD[0] ACK64# GND
23 GND 3.3 V AD[4] AD[3] 5 V AD[2] GND
22 GND AD[7] GND 3.3 V AD[6] AD[5] GND
21 GND 3.3 V AD[9] AD[8] M66EN C/BE[0]# GND
20 GND AD[12] GND V(I/O) AD[11] AD[10] GND
19 GND 3.3 V AD[15] AD[14] GND AD[13] GND
18 GND SERR# GND 3.3 V PAR C/BE[1]# GND
17 GND 3.3 V IPMB_SCL
1
IPMB_SDA
1
GND PERR# GND
16 GND DEVSEL# GND V(I/O) STOP# LOCK# GND
15 GND 3.3 V FRAME# IRDY# BD_SEL# TRDY# GND
14 GND (KEY) (KEY) (KEY) (KEY) (KEY) GND
13 GND (KEY) (KEY) (KEY) (KEY) (KEY) GND
12 GND (KEY) (KEY) (KEY) (KEY) (KEY) GND
11 GND AD[18] AD[17] AD[16] GND C/BE[2]# GND
10 GND AD[21] GND 3.3 V AD[20] AD[19] GND
9 GND C/BE[3]# IDSEL
7
AD[23] GND AD[22] GND
8 GND AD[26] GND V(I/O) AD[25] AD[24] GND
7 GND AD[30] AD[29] AD[28] GND AD[27] GND
6 GND REQ0#
6
3.3 V CLK0
6
AD[31] GND
5 GND BRSVP1A5 BRSVP1B5 PCI_RST# GND GNT0#
6
GND
4 GND IPMB_PWR HEALTHY# V(I/O) INTP INTS GND
3 GND INTA# INTB# INTC# 5 V INTD# GND
2 GND TCK 5 V TMS TDO TDI GND
1 GND 5 V -12 V TRST# +12 V 5 V GND
NOTES:
1.
1. The CompactPCI specification defines this pin as GND for system slots. This pin corresponds to the BD_SEL# signal in non-
system slots. Intel systems that implement CMM slots treat this pin as a BD_SEL# in system slots as well as non-system slots.
This signal is routed as a slot-specific signal to the CMM(s). BD_SEL# in slot n is connected to N_BDSn# on the CMM(s).
Third party system slot boards may treat this pin as GND or may not connect to this pin.
2. This pin is defined as GND in PICMG 2.0 R3.0. PICMG* 2.16. R1.0 redefined this pin as PCI_PRESENT# for all PICMG 2.16
compliant slots.
3. HEALTHY# is routed as a slot-specific signal to the CMM(s). HEALTHY# in slot n is connected to N_HLYn# on the CMM(s).
4. The JTAG signals (TCK, TMS, TDO, and TDI) are not routed on the ZT 5085 midplane .
5. The CLK0, REQ0#, and GNT0# signals are connected between the pair of multi-purpose slots.
6. The CompactPCI specification defines this pin as GND for system slots. This pin corresponds to the IDSEL pin in peripheral
slots. Intel RSS slots use this pin as IDSEL in order to support peripheral boards in RSS slots. The ZT 5085 midplane
connects this pin to AD20 in slots 9 and 10, and AD24 in slots 11 and 12. Third party system slot boards may ground this pin,
which would render the bus inoperable.
7. PCI_RST is connected to a 1K pulldown resistor in slots 7, 8, 16, and 17. This holds the signal into a reset state and disables
the PCI bus. Other node slots tie to these signals to disable the PCI bus.