Intel MAX 10 JTAG, Руководство пользователя

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4. I/O Voltage Support in the JTAG Chain
A JTAG chain can contain several Intel FPGA and non-Intel FPGA devices.
The
TDO
pin of a device drives out at the voltage level according to the V
CCIO
of the
device. The devices can interface with each other although the devices may have
different V
CCIO
levels.
For example, a device with 3.3-V V
CCIO
can drive to a device with 5.0-V V
CCIO
because
3.3 V meets the minimum VIH on transistor-to-transistor logic (TTL)-level input for the
5.0-V V
CCIO
device.
Intel MAX 10 devices can support 1.5-, 1.8-, 2.5-, or 3.3-V input levels, depending on
the V
CCIO
voltage of I/O Bank 1B.
To interface the
TDI
and
TDO
lines of the JTAG pins of devices that have different
V
CCIO
levels, insert a level shifter between the devices. If possible, construct the JTAG
chain where device with a higher V
CCIO
level drives to a device with an equal or lower
V
CCIO
level. In this setup, you only require a level shifter for shifting the
TDO
level to a
level JTAG tester accept.
Figure 3. JTAG Chain of Mixed Voltages and Level Shifters
2.5-V
VCCIO
1.8-V
VCCIO
1.8-V
VCCIO
TDI
TDO
Tester
Shift TDO to Level
Accepted by Tester
if Necessary
Must be 5.0-V
Tolerant
Must be 3.3-V
Tolerant
Must be 2.5-V
Tolerant
1.5-V
VCCIO
Must be 1.8-V
Tolerant
Level
Shifter
3.3-V
VCCIO
5.0-V
VCCIO
UG-M10JTAG | 2019.05.10
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