Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors—Expansion Bus
Controller
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Developer’s Manual
August 2006
658
Order Number: 306262-004US
12.4.1.4
Expansion Bus Interface Configuration
There are eight registers called the Timing and Control (EXP_TIMING_CS) Registers
that define the operating mode for each chip select. When designing with the
Expansion Bus Interface, placing the devices on the correct chip selects is required.
Chip Select 0 through 7 can be configured to operate with devices that require an Intel,
Synchronous Intel, Micron* ZBT or Motorola* Micro-Processor style bus accesses.
These chip selects can be configured to operate in a multiplexed or a simplex mode of
operation for either Intel- or Motorola-style bus accesses. Additionally, Chip Select 4
through 7 can be configured to generate Texas Instruments HPI-style bus accesses.
The mode of operation (Intel, Motorola, TI* HPI*, or Synchronous Intel, Micron ZBT) is
set by bits 15,14, and 8 of each Timing and Control (EXP_TIMING_CS) Register.
shows the possible settings for the Cycle Type selection using
bits 15, 14, and 8 of the Timing and Control (EXP_TIMING_CS) Register.
Once the cycle type has been determined, the mode of operation must be set. There
are two configurable modes of operation for each chip select, multiplexed and non-
multiplexed. Bit 4 of the Timing and Control (EXP_TIMING_CS) Registers is used to
select this mode. If bit 4 of the Timing and Control (EXP_TIMING_CS) Register is set to
logic 1, the access mode for that Chip Select is multiplexed. Likewise, if bit 4 of the
Timing and Control (EXP_TIMING_CS) Register is cleared to logic 0, the access mode
for that Chip Select is non-multiplexed. For Synchronous Intel, Micron ZBT memories
bit 4 must be programmed to logic 0. Multiplexed and non-multiplexed can imply
different operations depending upon the Cycle Type that is selected. For more
information refer to section
“Expansion Bus Outbound Timing Diagrams” on page 665
The size of the data bus for each device connected to the Expansion bus must be
configured. The data bus size is selected on a per-chip-select basis, allowing the most
flexibility when connecting devices to the Expansion bus. There are three valid
selections that can be configured for each data bus size, 8-bit, 16-bit, or 32 bit. Bit 0
and bit 2 of each Timing and Control (EXP_TIMING_CS) Register is used to select the
data bus size on a per-chip-select basis. For more information refer to
Level Definition for each of the Timing and Control Registers” on page 705
. One special
case for the data bus width selection is for chip select 0. Chip select 0 (data bus width)
is selected by the value contained on Expansion Bus Address bit 0 and bit 7 at the
assertion of PLL_LOCK. When PLL_LOCK is deasserted, Expansion Bus Address bit 0
and 7 will be captured into Timing and Control (EXP_TIMING_CS) Register bit 0 and 2
for Chip Select 0. This feature allows either an 8-bit, 16-bit or 32-bit flash device to be
connected to the Expansion Bus Interface for a boot device.
Byte write
16-bit
10
10
AHB data bus [15:8] = Expansion data bus [15:8],
EX_BE_N = 0xD
Byte write
16-bit
11
10
AHB data bus [7:0] = Expansion data bus [7:0],
EX_BE_N = 0xE
Byte write
32-bit
00
00
AHB data bus [31:24] = Expansion data bus
[31:24], EX_BE_N = 0x7
Byte write
32-bit
01
00
AHB data bus [23:16] = Expansion data bus
[23:16], EX_BE_N = 0xB
Byte write
32-bit
10
00
AHB data bus [15:8] = Expansion data bus [15:8],
EX_BE_N = 0xD
Byte write
32-bit
11
00
AHB data bus [7:0] = Expansion data bus [7:0],
EX_BE_N = 0xE
Table 220.
Expansion Bus Address and Data Byte Steering (Sheet 3 of 3)
AHB Bus
Cycle
Device Width
Connected to
Expansion Bus
(8-bit or 16-bit
or 32-bit)
AHB Address
Value
(AHB_ADDR[1:0]
)
Expansion Bus
Address Value
(EX_ADDR[1:0]
)
Data Location Translation Between Expansion
Data Bus and AHB Data Bus
