Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя, Страница: 913 / 1898

3:14 Volume 3: Instruction Reference
add
add — Add
Format: (
qp
) add
r
1
=
r
2
,
r
3
register_form A1
(
qp
) add
r
1
=
r
2
,
r
3
, 1 plus1_form, register_form A1
(
qp
) add
r
1
=
imm
,
r
3
pseudo-op
(
qp
) adds
r
1
=
imm
14
,
r
3
imm14_form A4
(
qp
) addl
r
1
=
imm
22
,
r
3
imm22_form A5
Description:
The two source operands (and an optional constant 1) are added and the result placed
in GR
r
1
. In the register form the first operand is GR
r
2
; in the imm_14 form the first
operand is taken from the sign-extended
imm
14
encoding field; in the imm22_form the
first operand is taken from the sign-extended
imm
22
encoding field. In the imm22_form,
GR
r
3
can specify only GRs 0, 1, 2 and 3.
The plus1_form is available only in the register_form (although the equivalent effect in
the immediate forms can be achieved by adjusting the immediate).
The immediate-form pseudo-op chooses the imm14_form or imm22_form based on the
size of the immediate operand and the value of
r
3
.
Operation: if (PR[ qp ]) {
check_target_register( r
1
);
if (register_form) // register form
tmp_src = GR[ r
2
];
else if (imm14_form) // 14-bit immediate form
tmp_src = sign_ext( imm
14
, 14);
else // 22-bit immediate form
tmp_src = sign_ext( imm
22
, 22);
tmp_nat = (register_form ? GR[ r
2
].nat : 0);
if (plus1_form)
GR[ r
1
] = t GR[ r
3
] + 1;
else
GR[ r
1
] = t GR[ r
3
];
GR[ r
1
].nat = tmp_nat || GR[ r
3
].nat;
}
Interruptions:
Illegal Operation fault