Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя, Страница: 859 / 1898

Volume 2, Part 2: External Interrupt Architecture 2:611
the time-out value. In this case the ITM has to be adjusted in order for the next ITM to
be accurate. The following algorithm could be used to adjust the next ITM before
returning from the timer interrupt handler.
for (;;) {
itm_next = it timeout (read current ITC - read current ITM);
if (itm_next < current ITC) {
/* we missed the next interrupt already, continue */
} else {
set_itm(itm_next);
break;
}
}
where
itm_next
was initialized to current ITC +
timeout_delta
, and
set_itm
in Itanium
architecture-based assembly would look like:
.global set_itm
.proc set_itm
set_itm:
alloc r18=ar.pfs,1,0,0,0
mov cr.itm=r32
;;
srlz.d
br.ret.sptk b0
;;
.endp set_itm
10.5.6 Resource Utilization Counter Usage Example
The Itanium architecture provides a 64-bit counter to provide information on how many
execution cycles a given logical processor is getting. It is similar to the Interval Timer
(ITC, AR 44), except that it is clocked only when the logical processor is active.
Optimizations such as hardware multi-threading and processor virtualization may cause
a logical processor to sometimes be inactive. The Resource Utilization Counter allows
for better cycle accounting for logical processors, given these types of optimizations.
RUC should only be written by Virtual Machine Monitors; other Operating Systems
should not write to RUC, but should only read it.
10.5.7 Local Redirection Example
The Local Redirection Registers (LRR0-1) serves to steer external signal-based
interrupts that are directly connected to the processor. LRR0 and LRR1 control the
external interrupt signals (pins) referred to as Local Interrupt 0 (LINT0) and Local
Interrupt 1 (LINT1) respectively. The example below shows how to mask interrupt
delivery on LINT0.
movl r18=(1<<16)
;;
mov cr.lrr0=r18
;;
srlz.d // srlz.d is required after LRR write to ensure write effect
Note: LINT0 and LINT1 pins are not required to be supported. Writes to LRR0-1 con-
trol registers would have not effect, and reads from LRR0-1 control registers
would return 0.