Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя, Страница: 802 / 1898

2:554 Volume 2, Part 2: Context Management
two “disabled” bits, PSR.dfl and PSR.dfh, are accessible to the privileged software
alone. Setting a “disabled” bit causes a fault into the disabled-fp vector upon first use
(read or write) of the corresponding register set.
As mentioned earlier, an involuntary kernel entry (e.g. interruption) needs to preserve
all scratch floating-point registers. Instead of blindly always spilling all registers, state
spills can be conditionalized upon the “modified” bits in the PSR. Additionally, the
“disabled” bits allow a deferred, or lazy, approach to both spills and fills. This is
particularly useful for “on demand” state motion in an involuntary interruption handler
that does not use many floating-point registers. To perform deferred spills on the high
set, the handler sets PSR.dfh immediately upon entry. Any reference to a floating-point
register in the high set will then fault into the disabled-fp vector which spills the
corresponding state to a prearranged store before allowing use within the handler. Lazy
state restoration is performed in a similar manner: the handler sets the “disabled” bit
just before exit, causing the first reference by the interrupted context to the disabled
set to fault into the kernel’s disabled floating-point vector which can then restore the
appropriate state. Note the importance of agreeing upon prearranged stores for
deferred spill/fill policies and the need for a mechanism to communicate a past fill or
spill.
At process or thread context switches all preserved floating-point registers need to be
context switched. The higher (scratch) set is also managed here if the context-switch
was occasioned by an involuntary interruption (e.g. timer interrupt) which did not
already spill the higher set. Use of the “modified” bits by the OS to determine if the
appropriate register set is “dirty” with previously unsaved data can help avoid needless
spills and fills.
The “modified” bits are intentionally accessible through the user mask so that a user
process can provide hints to the OS code about its register liveness requirements.
Clearing PSR.mfh, for instance, suggests that the user process does not see the higher
register set as containing useful data anymore.
4.3 Preserving ALAT Coherency
As described in Section 4.4.5.3, “Detailed Functionality of the ALAT and Related
Instructions” on page 1:65 , software is required to explicitly invalidate the entire ALAT
using the
invala
instruction whenever the virtual to physical register mapping is
changed. Typically this occurs when the
clrrb
instruction is used, when a synchronous
backing store switch is performed (e.g. in a user-level or kernel thread context switch),
or when software “discontinuously” remaps the register to backing store mapping by
resetting BSPSTORE (e.g. by calling
longjmp()
).
When returning to a user-process after servicing an involuntary interruptions, an
Itanium architecture-based operating system is required to invalidate the entire ALAT
using the
invala
instruction. This is required because the operating system may have
targeted advanced loads at scratch registers, and thereby altered the user-visible ALAT
state.
When returning from a system call, however, full ALAT invalidations can be avoided by
using
invala.e
instructions to selectively invalidate ALAT entries of all preserved
registers (GR4-7, FR2-5, and FR16-31), or by ensuring that these registers where