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Volume 2, Part 1: Processor Abstraction Layer
2:379
PAL_CACHE_PROT_INFO
Each
cache_protection
element has the following structure:
•
data_bits
–
Unsigned 8-bit integer denoting the number of data bits that each unit
of protection covers. For example, if the cache hardware generates 8 bits of ECC
per 64 bits of data,
data_bits
would be 64. This field is only valid if
t_d
is 0, 2, or 3.
•
tagprot_lsb
–
Unsigned 6-bit integer denoting the least-significant tag address bit
that this protection method covers. This field is only valid if
t_d
is 1, 2, or 3.
•
tagprot_msb
–
Unsigned 6-bit integer denoting the most-significant tag address bit
that this protection method covers. This field is only valid if
t_d
is 1, 2, or 3.
•
prot_bits
–
Unsigned 6-bit integer denoting the number of protection bits generated
for the field specified by the
t_d
element.
•
method
–
Unsigned 4-bit integer denoting the protection method, where:
All other values of
method
are reserved.
•
t_d
–
2-bit field denoting whether this protection method applies to the tag, the
data, or both. If over both, the tag and data unit could be concatenated with the
tag either to the left (more significant) or to the right (less significant) than a unit
of data. For the values of 2 and 3, the difference of
tagprot_msb
and
tagprot_lsb
indicates the number of tag bits that are protected with the data bits. The data bits
are described by the
data_bits
field below. This field is encoded as follows:
When obtaining cache information via this call, information for the data cache should be
obtained first, then if the
u
bit of the
config_info_1
parameter is not set, obtain the
information for the instruction cache.
Figure 11-6.
config_info_3
Return Value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
cache_protection[4]
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
cache_protection[5]
Figure 11-7.
cache_protection
Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
t_d
method
prot_bits
tagprot_msb
tagprot_lsb
data_bits
Table 11-72.
method
Values
Value Description
0
no ECC or parity protection
1
odd parity protection
2
even parity protection
3 ECC
protection
Table 11-73.
t_d
Values
Value
Description
0
Data protection
1
Tag protection
2
Tag+data protection (tag is more significant)
3
Data+tag protection (data is more significant)
Содержание ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
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Страница 808: ...2 560 Volume 2 Part 2 Context Management ...
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Страница 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Страница 1564: ...4 262 Volume 4 Base IA 32 Instruction Reference LES Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1565: ...Volume 4 Base IA 32 Instruction Reference 4 263 LFS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1568: ...4 266 Volume 4 Base IA 32 Instruction Reference LGS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1583: ...Volume 4 Base IA 32 Instruction Reference 4 281 LSS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Страница 1663: ...Volume 4 Base IA 32 Instruction Reference 4 361 SHL SHR Shift Instructions See entry for SAL SAR SHL SHR ...
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