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Volume 2, Part 1: Processor Abstraction Layer
2:279
Processor Abstraction Layer
11
This chapter defines the architectural requirements for the
Processor Abstraction
Layer (PAL)
for all processors based on the Itanium architecture. It is intended for
processor designers, firmware/BIOS designers, system designers, and writers of
diagnostic and low level operating system software.
PAL is part of the Itanium processor architecture and its goal is to provide a consistent
firmware interface to abstract processor implementation-specific features.
The objectives of this chapter are to define:
• The architectural behavior and interface requirements for processor testing,
configuration and error recovery. This includes the hardware entrypoints into PAL
and the PAL interfaces to platform firmware and system software.
• A set of boot and runtime PAL procedures to access processor
implementation-specific hardware and to return information about processor
implementation-dependent configuration.
• A computing environment for both PAL entrypoints and procedures such that:
• Memory used by PAL procedures is allocated by the caller of PAL procedures.
• PAL code runs little endian.
• PAL interface is as endian neutral as possible.
• PAL is Itanium architecture-based code.
• PAL code runs at privilege level 0.
• PAL procedures can be called without backing store, except where
memory-based parameters are returned.
• The processor and platform hardware requirements for PAL. This includes
minimizing PAL dependencies on platform hardware and clearly stating where those
dependencies exist.
• A PAL interface and requirements to support firmware update and recovery.
11.1
Firmware Model
As shown in
, Itanium architecture-based firmware consists of several major
components: Processor Abstraction Layer (PAL), System Abstraction Layer (SAL),
Unified Extensible Firmware Interface (UEFI) and Advanced Configuration and Power
Interface (ACPI). PAL, SAL, UEFI and ACPI together provide processor and system
initialization for an operating system boot. PAL and SAL provide machine check abort
handling. PAL, SAL, UEFI and ACPI provide various run-time services for system
functions which may vary across implementations. The interactions of the various
services that PAL, SAL, UEFI and ACPI provide are illustrated in
In the context of this model and throughout the rest of this chapter, the System
Abstraction Layer (SAL) is a firmware layer which isolates operating system and other
higher level software from implementation differences in the platform, while PAL is the
firmware layer that abstracts the processor implementation.
Содержание ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
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Страница 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 12: ...1 1 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part I Application Architecture Guide ...
Страница 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Страница 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Страница 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Страница 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
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Страница 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 249: ...2 1 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part I System Architecture Guide ...
Страница 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Страница 380: ...2 132 Volume 2 Part 1 Interruptions ...
Страница 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Страница 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Страница 749: ...2 501 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part II System Programmer s Guide ...
Страница 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Страница 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Страница 808: ...2 560 Volume 2 Part 2 Context Management ...
Страница 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Страница 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Страница 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Страница 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
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Страница 941: ...3 42 Volume 3 Instruction Reference cmp illegal_operation_fault PR p1 0 PR p2 0 Interruptions Illegal Operation fault ...
Страница 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Страница 1191: ...3 292 Volume 3 Pseudo Code Functions Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
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Страница 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Страница 1564: ...4 262 Volume 4 Base IA 32 Instruction Reference LES Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1565: ...Volume 4 Base IA 32 Instruction Reference 4 263 LFS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1568: ...4 266 Volume 4 Base IA 32 Instruction Reference LGS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1583: ...Volume 4 Base IA 32 Instruction Reference 4 281 LSS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Страница 1663: ...Volume 4 Base IA 32 Instruction Reference 4 361 SHL SHR Shift Instructions See entry for SAL SAR SHL SHR ...
Страница 1668: ...4 366 Volume 4 Base IA 32 Instruction Reference SIDT Store Interrupt Descriptor Table Register See entry for SGDT SIDT ...
Страница 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Страница 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Страница 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...