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Volume 2, Part 1: Debugging and Performance Monitoring
2:151
Debugging and Performance Monitoring
7
Processors based on the Itanium architecture provide comprehensive debugging and
performance monitoring facilities for both IA-32 and Itanium instructions. This chapter
describes the debug registers, performance monitoring registers and their
programming models. The debugging facilities include several data and instruction
break point registers, single step trap, breakpoint instruction fault, taken branch trap,
lower privilege transfer trap, instruction and data debug faults. The performance
monitoring facilities include two sets of registers to configure and collect various
performance-related statistics.
7.1
Debugging
Several Data Breakpoint Registers (DBR) and Instruction Breakpoint Registers (IBR)
are defined to hold address breakpoint values for data and instruction references. In
addition the following debugging facilities are supported:
•
Single Step trap
– When PSR.ss is 1, successful execution of each Itanium
instruction results in a Single Step trap. When PSR.ss is 1 or EFLAG.tf is 1,
successful execution of each IA-32 instruction results in an
IA_32_Exception(Debug) single step trap. After the trap, IIP and IPSR.ri point to
the next instruction to be executed. IIPA and ISR.ei point to the trapped
instruction. See
for complete single stepping behavior.
•
Break Instruction fault
– execution of a
break
instruction results in a Break
Instruction fault. IIM is loaded with the immediate operand from the instruction.
IIM values are defined by software convention.
break
can be used for profiling,
debugging and entry into the operating system (although Enter Privileged Code
(
epc
) is recommended since it has lower overhead). Execution of the IA-32 INT 3
(break) instruction results in a IA_32_Exception(Break) trap.
•
Taken Branch trap
– When PSR.tb is 1, a Taken Branch trap occurs on every
taken Itanium branch instruction. When PSR.tb is 1, a IA_32_Exception(Debug)
taken branch trap occurs on every taken IA-32 branch instruction (CALL, Jcc, JMP,
RET, LOOP). This trap is useful for debugging and profiling. After the trap, IIP and
IPSR.ri point to the branch target instruction and IIPA and ISR.ei point to the
trapping branch instruction.
•
Lower Privilege Transfer trap
– When PSR.lp bit is 1, and an Itanium branch
demotes the privilege level (numerically higher), a Lower Privilege Transfer trap
occurs. This trap allows for auditing of privilege demotions, for example to remove
permissions which were granted to higher privilege code. After the trap, IIP and
IPSR.ri point to the branch target and IIPA and ISR.ei point to the trapping branch
instruction. IA-32 instructions can not raise this trap.
•
Instruction Debug faults
– When PSR.db is 1, any Itanium instruction memory
reference that matches the parameters specified by the IBR registers results in an
Instruction Debug fault. Instruction Debug faults are reported even if Itanium
instructions are nullified due to a false predicate. If PSR.id is 1, Itanium Instruction
Debug faults are disabled for one instruction. The successful execution of an
Itanium instruction clears PSR.id. When PSR.db is 1, any IA-32 instruction memory
Содержание ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
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Страница 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 12: ...1 1 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part I Application Architecture Guide ...
Страница 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Страница 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Страница 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Страница 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Страница 230: ......
Страница 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 249: ...2 1 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part I System Architecture Guide ...
Страница 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Страница 380: ...2 132 Volume 2 Part 1 Interruptions ...
Страница 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Страница 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Страница 749: ...2 501 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part II System Programmer s Guide ...
Страница 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Страница 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Страница 808: ...2 560 Volume 2 Part 2 Context Management ...
Страница 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Страница 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Страница 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Страница 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
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Страница 941: ...3 42 Volume 3 Instruction Reference cmp illegal_operation_fault PR p1 0 PR p2 0 Interruptions Illegal Operation fault ...
Страница 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Страница 1191: ...3 292 Volume 3 Pseudo Code Functions Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Страница 1296: ......
Страница 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Страница 1564: ...4 262 Volume 4 Base IA 32 Instruction Reference LES Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1565: ...Volume 4 Base IA 32 Instruction Reference 4 263 LFS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1568: ...4 266 Volume 4 Base IA 32 Instruction Reference LGS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1583: ...Volume 4 Base IA 32 Instruction Reference 4 281 LSS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Страница 1663: ...Volume 4 Base IA 32 Instruction Reference 4 361 SHL SHR Shift Instructions See entry for SAL SAR SHL SHR ...
Страница 1668: ...4 366 Volume 4 Base IA 32 Instruction Reference SIDT Store Interrupt Descriptor Table Register See entry for SGDT SIDT ...
Страница 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Страница 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Страница 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...