Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя, Страница: 162 / 1898

Volume 1, Part 2: Memory Reference 1:151
Since the latency of a load is two cycles, the
sub
instruction will stall until cycle three.
To avoid a stall, the compiler can move the load earlier in the schedule so that the
machine can perform useful work each cycle:
ld4 r2=[r3] // Cycle 0
add r7=r6,1
add r13=r25,r27
cmp.eq p1,p2=r12,r23;;
add r11=r13,r29;; // Cycle 1
sub r4=r2,r11 // Cycle 2
In this code, there are enough independent instructions to move the load earlier in the
schedule to make better use of the functional units and reduce execution time by one
cycle.
Now suppose that the original code sequence contained an ambiguous memory
dependency between a store instruction and the load instruction:
add r7=r6,1 // Cycle 0
add r13=r25,r27
cmp.ne p1,p2=r12,r23;;
st4 [r29]=r13 // Cycle 1
ld4 r2=[r3] ;;
sub r4=r2,r11 // Cycle 3
In this case, the load cannot be moved past the store due to the memory dependency.
Stores will cause data dependencies if they cannot be disambiguated from loads or
other stores.
In the absence of other architectural support, stores can prevent moving loads and
their dependent instructions: The following C language statements could not be
reordered unless
ptr1
and
ptr2
were statically known to point to independent memory
locations:
*ptr1 = 6;
x = *ptr2;
3.4 Using Speculation in the Intel
®
Itanium
®
Architecture to Overcome Dependencies
Both data and control dependencies constrain optimization of program code. The
Itanium architecture provides support for two basic techniques used to overcome
dependencies:
• Data speculation : Allow a load and possibly its uses to be moved across
ambiguous memory writes.
• Control speculation : Allows a load and possibly its uses to be moved across a
branch on which the load is control dependent.
These techniques are used to hide load latencies and reduce execution time.