Intel Itanium 9150M, Руководство пользователя, Страница: 277 / 420

3:268 Volume 3: Instruction Reference
tpa
tpa — Translate to Physical Address
Format: (
qp
) tpa
r
1
=
r
3
M46
Description:
The physical address for the virtual address specified by GR
r
3
is obtained and placed in
GR
r
1
.
When PSR.dt is 1, the DTLB and the VHPT are searched for the virtual address specified
by GR
r
3
and the region register indexed by GR
r
3
bits {63:61}. If a matching present
translation is found the physical address of the translation is placed in GR
r
1
. If a
matching present translation is not found the appropriate TLB fault is taken.
When PSR.dt is 0, only the DTLB is searched, because the VHPT walker is disabled. If no
matching present translation is found in the DTLB, an Alternate Data TLB fault is raised
if psr.ic is one or a Data Nested TLB fault is raised if psr.ic is zero.
If this instruction faults, then it will set the non-access bit in the ISR. The ISR read and
write bits are not set.
This instruction can only be executed at the most privileged level, and when PSR.vm is
0.
Operation: if (PR[ qp ]) {
itype = NON_ACCESS|TPA;
check_target_register(
r
1
);
if (PSR.cpl != 0)
privileged_operation_fault(itype);
if (GR[ r
3
].nat)
register_nat_consumption_fault(itype);
GR[ r
1
] = tlb_translate_nonaccess(GR[ r
3
], itype);
GR[ r
1
].nat = 0;
}
Interruptions:
Illegal Operation fault Alternate Data TLB fault
Privileged Operation fault VHPT Data fault
Register NaT Consumption fault Data TLB fault
Unimplemented Data Address fault Data Page Not Present fault
Virtualization fault Data NaT Page Consumption fault
Data Nested TLB fault