Intel Itanium 9150M, Руководство пользователя, Страница: 231 / 420

3:222 Volume 3: Instruction Reference
pshl
pshl — Parallel Shift Left
Format: (
qp
) pshl2
r
1
=
r
2
,
r
3
two_byte_form, variable_form I7
(
qp
) pshl2
r
1
=
r
2
, count
5
two_byte_form, fixed_form I8
(
qp
) pshl4
r
1
=
r
2
,
r
3
four_byte_form, variable_form I7
(
qp
) pshl4
r
1
=
r
2
, count
5
four_byte_form, fixed_form I8
Description:
The data elements of GR
r
2
are each independently shifted to the left by the scalar shift
count in GR
r
3
, or in the immediate field count
5
. The low-order bits of each element are
filled with zeros. The shift count is interpreted as unsigned. Shift counts greater than 15
(for 16-bit quantities) or 31 (for 32-bit quantities) yield all zero results. The results are
placed in GR
r
1
.
Operation: if (PR[ qp ]) {
check_target_register( r
1
);
shift_count = (variable_form ? GR[ r
3
] : count
5
);
tmp_nat = (variable_form ? GR[ r
3
].nat : 0);
if (two_byte_form) { // two_byte_form
if (shift_count u> 16)
shift_count = 16;
GR[ r
1
]{15:0} = GR[ r
2
]{15:0} << shift_count;
GR[ r
1
]{31:16} = GR[ r
2
]{31:16} << shift_count;
GR[ r
1
]{47:32} = GR[ r
2
]{47:32} << shift_count;
GR[ r
1
]{63:48} = GR[ r
2
]{63:48} << shift_count;
} else { // four_byte_form
if (shift_count u> 32)
shift_count = 32;
GR[ r
1
]{31:0} = GR[ r
2
]{31:0} << shift_count;
GR[ r
1
]{63:32} = GR[ r
2
]{63:32} << shift_count;
}
GR[ r
1
].nat = GR[ r
2
].nat || tmp_nat;
}
Interruptions:
Illegal Operation fault
Figure 2-39. Parallel Shift Left Examples
GR r
2
:
GR r
1
:
Shift Left
pshl2
0
0
0
0
0 0 0 0
GR r
2
:
GR r
1
:
pshl4
0
0
0 0