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Содержание INTELLEC

Страница 1: ...INTELLECT DOUBLE DENSITY DISKETTE OPERATING SYSTEM HARDWARE REFERENCE MANUAL Copyright 1977 Intel Corporation Intel Corporation 3065 Bowers Avenue Santa Clara California95051 Order Number 9800422 01...

Страница 2: ...y for the use of any circuitry other than circuitry embodied in an Intel product No other circuit patent licenses are implied Intel software products are copyrighted by and shall remain the property o...

Страница 3: ...cates with the INTELLEC Microcomputer Development System and how it functions internally Refer to the ISIS II System User s Guide order number 98 306 for complete instructions on how to operate the Di...

Страница 4: ...TA GENERATOR 4 6 4 2 3 SERIAL DATA CLOCK SYNCHRONIZATION 4 10 4 2 4 CYCLIC REDUNDANCY CHECK CRC 4 10 4 2 5 BUS CONTROL 4 13 4 3 SCHEMATICS PIN LISTS INTERFACE BOARD 4 15 THE DISKETTE DRIVES 5 1 5 1 FU...

Страница 5: ...TIONAL BLOCK DIAGRAM 3 2 3 2 3001 MICROPROGRAM CONTROL UNIT FUNCTIONAL BLOCK DIAGRAM 3 6 3 3 3002 CENTRAL PROCESSING ELEMENT FUNCTIONAL BLOCK DIAGRAM 3 14 3 4 SCHEMATIC DRAWING CHANNEL BOARD 3 21 4 IN...

Страница 6: ...CHECKER 6 16 6 14 READ NEXT MEMORY WORD 6 17 6 15 WRITE DATA FIELD 6 18 6 16 WRITE CURRENT CHECK 6 19 6 17 TIME OUT 6 20 6 18 ADDRESS MARK DETECT 6 21 6 19 HEAD STEPPER 6 22 6 20 READ DISK BYTE 6 23...

Страница 7: ...FIELD BITS 3 12 3 5 K BUS INPUT SELECTION 3 13 3 6 PIN LIST P1 BUS CONNECTOR 3 17 3 7 PIN LIST P2 CONTROLLER CONNECTOR 3 19 4 THE INTERFACE BOARD 4 1 PIN LIST P1 BUS CONNECTOR 4 16 4 2 PIN LIST P2 CON...

Страница 8: ...w Jl...

Страница 9: ...the specified operations The Channel Board also monitors Diskette System status and error conditions and organizes these indications into result type and result byte words that can be read by a CPU i...

Страница 10: ...cc D o 3 00 s UJ CO CO LLJ f UJ V Q 0 3 O 1 2...

Страница 11: ...1 DISKETTE DRIVE PERFORMANCE SPECIFICATIONS Capacity formatted Data Transfer Rate Access Time Average Access Time Rotational Speed Average Latency Recording Mode Per Disk Per Track Track to Track Sett...

Страница 12: ...tor address marks sector headers and data sectors The index mark and sector address marks are recorded with unique clock patterns requiring the con troller circuitry to accumulate the unique clock pat...

Страница 13: ...tween formatting and updating of individual data fields V Gap4 Pre lndex Gap The 338 bytes between the last Data field on a track and the Index Address Mark are defined as Gap 4 Pre lndex Gap Initiall...

Страница 14: ...rator polynomial G X For all fields recorded on a diskette this generator polynomial is t I y 1R i V 1 i V R i 1 b X X I D X 1 X 1 75 x When a field is read back from a diskette the data bits from bit...

Страница 15: ...IMAL REPRESENTATION OF DATA BITS CLOCK BITS Figure 1 3 BYTE REPRESENTATION I BYTE 0 BYTE 1 2 3 4 5 6 7 8 9 10 11 12 13 I 14 15 16 BYTE 17 BIT CELL OOF BYTE 0 IS FIRST DATA TO BE SENT TO THE DRIVE WHEN...

Страница 16: ...E A M p p EACH PULSE IS A DISKETTE FLUX REVERSAL DATA BYTE D 2 1 1 X 4 us 3 us 3 us n n n D C D 0 1 0 0 1 0 V Figure 1 5 DATA BIT CLOCK BIT IF PRESENT BITCELL 2 us J1 TL DATA BIT TIME IF PRESENT Figu...

Страница 17: ...8 m Q oc D 0 u UJ CC X CO r uj uj 0 D K O z en 0 tt CD S 1 D V X r n 3 a m n Q Q DC 1 J O uj u LU I CQ o n CM CN CN O ui OC H J CO U ui CC H u CO cc UJ D u H m CO CN CC Q o S S cc 1 1 1 Q CC UJ Q Q Q...

Страница 18: ...TS HEXADECIMAL REPRESENTATION OF DATA BITS CLOCK BITS 0 0 0 0 1 1 0 0 Figure 1 8 INDEX ADDRESS MARK BIT CELL 5 BIT CELLO BIT CELL 1 BIT CELL 2 BIT CELL 3 A rvrvD ccc BIT CELL4 BIT CELL 5 BIT CELL 6 BI...

Страница 19: ...XADECIMAL REPRESENTATION OF DATA BITS CLOCK BITS 1 0 1 1 Figure 1 10 DATA ADDRESS MARK D C C n TL C n D n C n C J L BIT CELL 7 BIT CELLO BIT CELL 1 BIT CELL 2 BIT CELL 3 BIT CELL4 BIT CELL 5 DELETED D...

Страница 20: ...VIVO 031313C 9 H130 119 t 1130 119 1130 119 2 1130 119 L 1133 119 01133 119 1130 119 LJ 3 LJ 0 LJ a LJ 3 U LT 3 3 iaVIAI SS3HOOV VIVO OL L 3jnB d L L 0 L S1I9 3O13 sim viva dO NOIlVlN3S3Hd3d 1VIAII330...

Страница 21: ...an output instruction to a dedicated I O port address while the other three commands are the result of input instructions to dedicated ports The six channel commands are 1 Write memory address lower...

Страница 22: ...ll ones will be written into each of the 128 byte locations in the data field portion of this sector The sector address OE jg 14 Q W H be written into the sector address field of the second physical s...

Страница 23: ...Diskette Channel to begin executing the diskette operation specified in byte 2 instruction byte of the addressed IOPB System address bus BASE 2 System data bus Eight most significant bits of the 16 bi...

Страница 24: ...of CRC check bits will be generated as each sector is being read When the data address marks and all 128 data bytes of a sector have been read the generated CRC bits are compared with the 16 CRC bits...

Страница 25: ...y address that points to the first byte of an I O Parameter Block IOPB The second byte in the IOPB specifies one of the seven diskette operations seeSection 2 3 for IOPB format After the Diskette Syst...

Страница 26: ...of four different types of result byte see next paragraph associated with diskette BASE 1 LSB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 I t System address bus System data bus Type Code 00 I O Complete error bits 10...

Страница 27: ...S MARK 1 BYTE t 128 BYTES OF DATA DATA DELETED DATA ADDRESS MARK 1 BYTE 28 BYTES TWO BYTES OF CRC CHECK BITS ONE SECTOR Figure 2 1 SECTOR FORMAT C CLOCK D DATA FL__FT__Fl D D CLOCK 0 DATA Figure 2 2 D...

Страница 28: ...TELLEC System bus Depending on the particular channel command the CPU may also place relevant data on data lines DATO DAT of the INTELLEC System bus The CPU maintains the data lines until the Diskette...

Страница 29: ...el is being used with 8 bit systems or set logical 1 when being used with 16 bit systems This bit must be logical 0 when being used with the INTELLEC System an 8 bit system BYTE 1 2 3 4 5 6 7 IOPB FOR...

Страница 30: ...allowed but they must not go beyond the last sector on a track sector 52 that is an address error seeSection 2 4 will be indicated if starting sector address number of records 52 jQ Therefore the max...

Страница 31: ...ddress marks and write data with deleted data address marks operations DATA OVERRUN UNDERRUN ERROR This bit 4 indicates that the Diskette System controller was not able to service a byte transfer requ...

Страница 32: ...CRC error 1 bits are true it indicates that no address mark seeSection 1 2 was encountered for a full revolution of the diskette This usually indicates that the track hasnot been formatted r DATA MAR...

Страница 33: ...c Micro control unit MCU block Microprogram memory block Central processing element CPE block Data clock shift register SR block 1 Data flow control block The CHANNEL COMMAND BLOCK is responsiblefor r...

Страница 34: ...CPE BLOCK C INPU SI STATUS ERROR BITS CHANNEL COMMAND BLOCK ADRO ADR2 A 4 INPUT 4 DATA CLOCK SHIFT REGISTER BLOCK C DATA IN 3 C CLOCK 1 t CLOCK OUT V MICRO CONTROL UNIT MCU BLOCK A MASK BITS FUNCTION...

Страница 35: ...e values listed for that field and if the K Bus select line SO bit 9 of the current microinstruction is high logical 1 Refer toSec tion 3 2 4 for a more complete description of the 3002 CPE array inpu...

Страница 36: ...ut busses to determine the microinstruction execution sequence Saving and testing of carry output data from the central pro cessor CPE array j _ _ Control of carry shift input data to the CPE array Co...

Страница 37: ...3 line DAT3 indicating that the diskette controller is present INT is also passed to the Interface Board via pin P2 40 If a read result type command is being received output 1 from the decoder goes tr...

Страница 38: ...the 8234 section are the three least significant data outputs from the central pro cessing element CPE block that have been buffered and inverted the AO input is always high After having fetched the...

Страница 39: ...TPIIT 1 I OUTPUT r OUTPUT BUFFER OUTPUT BUFFER MICROPROGRAM ADDRESS REGISTER EN MCU OUTPUT ENABLE NEXT ADDRESS LOGIC pp2 PROGRAM PRi LATCH PRO OUTPUTS L _i J 7 FCQ FLAG FLAG LOGIC INPUT CONTROL T FQ F...

Страница 40: ...11 12 13 14 15 16 17 17 18 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SIGNAL MASKO MO MASK1 M1 MASK2 M2 MASK3 M3 MASK4 M4 MASK5 M5 MASK6 M6 MASK7 M7 SLKO SO SLK1 S1 OUTO OUT1 OUT2 INO IN1 IN2 FCO FC...

Страница 41: ...tch which provides various control signal levels based on the decoder outputs mentioned above and the mask bit field of the current microinstruction as shown on sheet 3 of the board schematic Section...

Страница 42: ...ata outputs DO D7 into the latch which drives the system data lines DATA8 DATAF This pulse loads CPE data outputs DO D7 into the latch which drives the system data bus lines DATAO DATA J This pulse lo...

Страница 43: ...rogram _ This pulse sets the LOAD latch on the Interface Board which causes the read write head on the selected unit to be loaded t This pulse resets the inhibit memory write latch A48 1 L This pulse...

Страница 44: ...e function bits are decoded the operands are selected by the internal multiplexers and the specified operation is performed Within each CPE data is stored in eleven scratchpad registers or the accumul...

Страница 45: ...MEMORY ADDRESS REGISTER MICRO FUNCTION DECODER DATA OUT J DO OUTPUT BUFFER AC REGISTER ARITHMETIC LOGIC SECTION MULTIPLEXER A i i i MULTIPLEXER B SCRATCHPAD REGISTERS R0 R9 T o M 1 M 0 MEMORY DATA IN...

Страница 46: ...on the 74151 multiplexer A30 3 which provides the least significant address control bit AGO to the 3001 MCU The carry input Cl to the least significant 3002 CPE A23 10 is provided by the flag control...

Страница 47: ...PO P1 and P2 inputs to the first clock shift register and the P2 and P3 inputs to the second clock shift regis ter are tied to ground The P3 input to the first shift register and the P1 input to the...

Страница 48: ...NTELLEC System outputs data to the diskette controller the data from lines DATO DAT7 isapplied to the 8212 bus driver at A25 DATS DATF isapplied to the 8212 at A24 Thedata on those lines are strobed i...

Страница 49: ...49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 SIGNAL i i f NO CONNECTION r 1 i j r ADRE ADRF ADRC ADRD ADRA ADRB ADR8 ADR9 ADR6 ADR7 ADR4 ADR5 ADR2 ADR3 ADRO ADR1 DATAE DATAF DATAC...

Страница 50: ...7 8 9 10 11 12 13 14 15 16 17 18 19 20 MK4 CLK1 MK1 SR CLK IN 1 CLKSRSTB USA SR CLK OUT TRACK OO USB MK0 DSK WRT PROT DRO DOR DR1 WRT ERR SR OUT SEL DR NRDY Mask bit 4 Diskette controller clock 1 Mask...

Страница 51: ...trol decoder 5 output Control decoder 4 output I Strobe memory data in Diskette controller clock 2 Stop diskette channel command Diskette controller addressed Control decoder output 7 Mask bit 3 Contr...

Страница 52: ...1 5 1 f 1 1 o L 0 0 if s 1 L rt 0 U 1 1 f1 j 1 L 1 wi a cw t J Y Y Y Y 1 1i i T O O lO O C J H i u t 3 f i 5 i f i 5 S P S g ISl ill t o I J I 1 s si l U T Q Q K 3 L O O U CJ K a g s d U a i 7 3 T J 0...

Страница 53: ...o CM 0 0 CO Q DC O 00 _l LJJ z z X u z DC Q O X o CO 0 3 O 3 22...

Страница 54: ...CO Q cc O CD _l UJ X U ti cc Q O I UJ X O CO O 3 23...

Страница 55: ...3 24 o Q 0 o cc o CO I o CD z cc Q O S 01 T O 3 O...

Страница 56: ...n be divided into five functional blocks _ x As shown in Figure 4 1 Disk drive control block i Serial data clock synchronization block __v Write clock generator block _ _ J Cyclic Redundancy Check CRC...

Страница 57: ...CKOO NEL DEC OUT n r r N DECODER CONTROL V MASK BITS MK 0 6 GATE L V OWER j XFER REQ CLK I CLOCK CLK2 MR RESET SELECTED RDCMD I OREAD WRTCMD ID WRT READ Rl READ INT RESET MEM WRT s STBMEMIN DISK DRIVE...

Страница 58: ...nput signals are driven and received in parallel to from each of the attached drive boxes drives 0 1 and drives 2 3 Only one drive is selected at any time however 4 2 1 Disk Drive Control _ J 2 i The...

Страница 59: ...vement If the head on the selected unit is loaded the output from the one shot will produce a 10 usec pulse on the STEP line as shown in Figure 4 2 After the head has been positioned over the proper t...

Страница 60: ...rted twice and passed to the channel board asthe WRT ERR signal at pin P2 18 WPROT lines pin J1 20 or J1 18 aremultiplexed by the 74153 multiplexer I C A31onsheet 3 and passed on to the channel board...

Страница 61: ...e density encoding data recovery is more susceptible to errors associated with magnetic bit shift To minimize the effects of read back bit shift the write data block includes precompensation cir cuitr...

Страница 62: ...J i i 1 1 i _J I 0 r u O j n 1 H LU CO D 1 1 D H Q 0 d 0 U 7 1 1 1 Z L_ U CN S 3 t CN i LU LL J Q LU I h co Q 1 1 1 E UJ D _J DC Z CD II 1 rf QQ Q 1 1 1 cc i I H m h co X 1 O E o o i s 1 UJ 1 00 DC O...

Страница 63: ...t r pc H t Q LU 2 LU _ CD LU DC 1 15 r a H UJ LU CO 1 fy 5 LU C D i i LU rf 1 LU n m 2 H 1 2 o H LU 2 01 UJ r L DC Z O 2 5 0 g oo O CO u UJ D L C5 5 Q E LL co _i if LU O J OO 2J t O CO oo 3 Jn LU O W...

Страница 64: ...onsists of linear circuitry which locks onto the recorded information and generates separate windows for data bits and clock bits Staying in synchronization with small slow variations in disk speed it...

Страница 65: ...L ERROR DETECTOR i LU CL 1 LOGIC i LU 1 Q LU CC CC 1 1 1 A fll 3 ro 1 CC cr c cc CL 2 C CC LL 2 i V Q a l a _i C LL CL _l _ O 1 Q Q LU N 5 CC Q Z 1 co Q LU CC 4 i 1 1 t _ z 2 1 d I 0 Q I cc Q g to co...

Страница 66: ...LL f CNS LH 5o 1 b Qco s L OC g 3S 0 co Q LU CO rr 1 LL i HCN LU 00 LU CC LU to LU OO OC 1 HCN 2 D o O 00 ii oo H 1 5 to 5 CO 0 to 00 H to cc i to o CN i Q in 00 to DC 05 LU I H LD LL O C3 03 CN Jre...

Страница 67: ...oes true the low level from the ER out put is clocked into the 7474 latch The high Q output from this latch drives the AZ line pin P2 41 to the Channel Board The microprogram controls the various oper...

Страница 68: ...ED signal pin P2 43 On the next BCLK pulse after BUSY goes true the 52 104 will drive the memory read MRDC or memory write MWTC command at pins P1 19 and P1 20 respectively depending upon whether a re...

Страница 69: ...driven through pin P1 23 XACK is reset when IORC or IOWC go false via the 7432 gate A38 8 The bus control block also hasan 8 position rotary switch which connectsthe interrupt line INT from the Channe...

Страница 70: ...O BUSY BREQ MRDC MWTC IORC IOWC XACK t L NO CONNECTION i ___ f t a r CCLK t NO CONNECTION INT6 INT7 INT4 INT5 INT2 INT3 INTO INT1 t NO CONNECTION i r FUNCTION _ _ i 1 Bus clock 9 803MHz System initial...

Страница 71: ...55 56 57 58 59 60 61 62 63 J J 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 SIGNAL i NO CONNECTION i I 1 v vf iL i j f FUNCTION l A J v T T j t V i v i K j J i v f V f K r f M...

Страница 72: ...est point Serial clock strobe Unit select bit A Track 00 detected Unit select bit B Mask bit 0 Disk write protected Drive 0 ready or Drive 2 ready Data overrun error Drive 1 ready or drive 3 ready Wri...

Страница 73: ...23 24 25 26 27 28 GND STEPO 1 GND STEP 2 3 GND DIR 0 1 GND DIR 2 3 GND WRT DAT 0 1 GND WRT DAT 2 3 GND WRT GT 0 1 GND WRT GT 2 3 GND WPROT 2 3 GND WPROT 0 1 GND READY 3 GND READY 1 GND READY 21 GND R...

Страница 74: ...e 0 Ground Drive inoperable write fault drive 0 1 Ground Drive inoperable write fault drive 2 3 Ground Read data unseparated drive 0 1 Ground Track 0 indicator drive 0 1 Ground Index indicator drive 2...

Страница 75: ...CTOR CONTINUED PIN 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 SIGNAL TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP FUNCTION Test Point 4 t i 1 v...

Страница 76: ...4 22 0...

Страница 77: ...O l X X J P f o I a t ia i Q u t 1 1 0 LiJ Z j M lO rtO l J in T in CSJ Cu S d if 3 i r ll vS lO in 1 n 7 VLS M r v S H s T sj J sS a ia 1 t 0 5 3 o lo 1 J l tT 1 rO I c i 3 2 S v uj u J S Ck UJ Q rl...

Страница 78: ...4 24...

Страница 79: ...Q QC O CQ UJ O LL CC UJ I z CC Q O UJ X O CO O 4 25...

Страница 80: ...4 26 O in 0 0 J CO Q cc O 00 UJ I z cc Q C I O CO O...

Страница 81: ...CD 0 JC Q cr o CO LU U LL DC LU h z DC Q U h 111 X O CO 3 O 4 27...

Страница 82: ......

Страница 83: ...transfer operations using only simple control commands 5 1 FUNCTIONAL DESCRIPTION The following paragraphs describe the major components of the FDD Electronics All electronic circuitry required to co...

Страница 84: ...ng disk diameter of 7 88 The FDD uses the IBM 2305830 type diskette or double density certified media such as Dysan 3740D or ITC 34 9000D 48 The disk has 77 concentric recording tracks spaced 02083 in...

Страница 85: ...t all times while power is applied to the unit and is not stopped for disk loading or unloading Since the time for the disk to reach the same speed as the spindle is negligible less than 2 seconds the...

Страница 86: ...skette can be written upon if so desired by masking the write protect hole 5 3 INTERFACE SPECIFICATION The following paragraphs describe the control and data interface lines shown in Figure 5 1 All si...

Страница 87: ...logic 0 5 WRITE FAULT RESET A logic 1 level on this line clears the Write Fault Latch This signal is not used on the SA 800 1 drive v s I I i 6 WRITE DATA REFER TO FIGURE 5 3 This line contains the d...

Страница 88: ...j i i i t L CD LU i LU CC CC D U CC S u i i LU LU nr h D LL CC FAULT WRITE READY D READY CM h z 1 o TRACK INDEX 1 u Q LU CC 0 o u Q LU CC WPROT Q LU CC O o o h z LU Q Z cc O LL Q LU I o Q D Q CO O I C...

Страница 89: ...ABLE PAIR J 7414 330 Figure 5 2 FDD DRIVER RECEIVER CIRCUITS Control and Data Lines from the FDD 1 INDEX This line gives an indication of the relative position of the disk by outputting a logic 1 puls...

Страница 90: ...SELECT HEAD LOAD N J WRITE ENABLE 11 tf 4i 60 msec maximum T T T 0 T 0 to 4 usec D 2 us D D D h 250 50 nsec Figure 5 3 WRITE DATA TIMING 58...

Страница 91: ...wer is on the door is closed and the diskette has reached its final speed The Unit Ready Interrupt assignments are accomplished by attaching the drive 0 or drive 1 signal adapter PCB i s 6 WRITE PROTE...

Страница 92: ...r D 250 50 nsec v D A When WRITE ENABLE IS HIGH read operation is implied During this time interval READ DATA CLOCK is to be mgored 3 Subject to 3 5 speed tolerance A For product acceptance purposes a...

Страница 93: ...is completely covered by an opaque material such as masking tape The diskettes shipped with the DOS have masked write protect notches removal of the opaque tape will yield a write protected diskette 5...

Страница 94: ...i...

Страница 95: ...MAL STIO RR IOPB FIN SEEK FMT REC VERF RD WDEL WT Initialization Mainline Load M A Lower Load M A Upper and Start I O Read Result Byte IOPB Loader Op Decode I O Finish Seek Format j Recalibrate __ j V...

Страница 96: ...INIT Entered from hardware reset switch or software reset command INITIALIZE INTERNAL FLAGS UNLOAD HEAD INPUT AND SAVE DRIVE READY STATUS JUMP TO ML 0 Figure 6 1 INITIALIZATION 62...

Страница 97: ...NPUT DRIVE READY STATUS NEW STATUS OLD STATUS UPDATE STATUS COMMAND PENDING SET STATUS CHANGE INTERRUPT INDEX PULSE TIME TO UNLOAD HEAD 7 UNLOAD HEAD JUMP TO COMMAND MAL STIO RR Figure 6 2 MAINLINE 6...

Страница 98: ...MAL INPUT INTELLEC DATA BUS TRANSFER DATA TO MEM ADD REG LO ACKNOWLEDGE INTELLEC BUS COMMAND JUMP TO ML D X Figure 6 3 LOAD MA LOWER 6 4...

Страница 99: ...STIO INPUT INTELLEC DATA BUS TRANSFER DATA TO MEM AND REG HI ACKNOWLEDGE INTELLEC BUS COMMAND JUMP TO IOPB 0 Figure 6 4 LOAD MA UPPER AND START I O 6 5...

Страница 100: ...TRANSFER RESULT BYTE TO INTELLEC BUS ACKNOWLEDGE INTELLEC BUS COMMAND LOAD HEAD LOAD CONSTANT FOR INDEX HEAD UNLOAD COUNT DOWN JUMP TO ML0 Figure 6 5 READ RESULT BYTE 6 6...

Страница 101: ...AD AND LOAD CHANNEL WORD READ AND LOAD I O WORD HEAD UNLOADED OR DIFFERENT DRIVE SELECT DRIVE LOAD HEAD CALL TIME OUT SUBROUTINE SELECTED DRIVE READY 7 READ AND LOAD NUMBER RECORDS WORD SET ERROR COND...

Страница 102: ...I O FIN FIN FIN 0 SET I O COMPLETE SET INTERRUPT JUMP TO ML 5 LOAD AND STORE ERROR BITS INHIBIT INTERRUPT 7 SET UP INTERRUPT CODE JUMP TO R R 3 Figure 6 7 I O FINISH 6 8...

Страница 103: ...SEEK SET ADD ERROR RESET SYNC CIRCUIT JUMP TO FIN CALL AM SUBROUTINE RESET CRC NETWORK SUBROUTINE JUMP TO FIN 0 CALL HEAD STEPPER SUBROUTINE Figure 6 8 SEEK 6 9...

Страница 104: ...CR TARGET TRACK I N I T I A L I Z E STEP COUNTER FOR 76 STEPS OUT INCR TARGET TRACK YES CALL HD STPR SUBROUTINE CALL AM SUBROUTINE RESET CRC NETWORK YES CALL ID SUBROUTINE CALL HD STPR SUBROUTINE TURN...

Страница 105: ...SECTOR REG EQUAL 1 YES LOAD SECTOR ADDR CALL WADD SUBROUTINE INCREMENT SECTOR REGISTER LOAD NEXT SECTOR FROM MEMORY LOAD DATA PATTERN JUMP TO FIN 0 TURN OFF WRITE GATE YES k NO EX r WRITE GAP 4 Figure...

Страница 106: ...RECALIBRATE SET TARGET REG TO ZERO CALL HD STPR SUBROUTINE Figure 6 10 RECALIBRATE 6 12...

Страница 107: ...TO FIN 0 CALL AM SUBROUTINE TURN OFF CRC NETWORK ID SUBROUTINE YES SECTORX NO EQUAL CALL HD STPR SUBROUTINE CALL AM SUBROUTINE FROM PAGE 6 14 SET AM ERROR JUMP TO FIN 0 YES SET DE LETED FLAG 1 YES _...

Страница 108: ...E DECREMENT BYTE COUNTER TO PAGE 6 13 DECREMENT BYTE COUNTER TRANSFER CHAR S TO MEMORY SET DELETED RECORD BIT NO JUMP TO FIN 0 CALL BYTE READ SUBROUTINE ODD BYTE SECTOR x NO COMPLETE YES r READ CHECK...

Страница 109: ...UTINE CALL AM SUBROUTINE RESET CRC NETWORK CALL HD STPR SUBROUTINE SET COUNTER FOR 18 BYTES OF GAP 2 CALL BYTE READ SUBROUTINE DECREMENT COUNTER TURN OFF WRITE GATE KH CALL WDAT SUBROUTINE JUMP TO FIN...

Страница 110: ...SECTOR EQUAL ZERO SECTOR N0 LESS THAN 53 7 TRACK LESS THAN 77 7 STARTING SECTOR PLUS NUMBER OF SECTORS LESS THAN 53 7 V YES RETURN TO CALLING ROUTINE if SET ADDRESS ERROR JUMP TO FIN 0 Figure 6 13 AD...

Страница 111: ...READ NEXT MEM WORD I r INCREMENT MEMORY ADDRESS REGISTER READ MEMORY DATA TO ACCUMULATOR i RETURN TO CALLING PROCEDURE Figure 6 14 READ NEXT MEMORY WORD 6 17...

Страница 112: ...ADD MARK WRITE 6 BYTES OF GAP 2 TURN ON CRC NETWORK WRITE ODD CHARACTER WRITE EVEN CHARACTER YES WRITE 1 BYTE OF GAP 3 WRITE CRC CHARACTERS RETURN TO CALLING PROCEDURE SET ERROR CONDITION JUMP TO FIN...

Страница 113: ...WRITE CURRENT CHECK WCURR CLEAR TRACK GTR 43 FLAG 1 r 3 SET TRACK GTR 43 FLAG RETURN TO CALLING ROUTINE Figure 6 16 WRITE CURRENT CHECK 6 19...

Страница 114: ...TIME OUT LOAD WAIT CONSTANT FIRE SINGLE SHOT HAS SINGLE SHOT TIMED OUT 7 DECREMENT WAIT CONSTANT RETURN TO IOPB ROUTINE Figure 6 17 TIME OUT 6 20...

Страница 115: ...IT CRC ARM READ SYNC LOGIC TURN ON CRC SET INDEX FLAG DOES CLOCK PORTION MATCH ID PATTERN 7 SELECTED DRIVE READY LOAD DATA PORTION SET NO AM ERROR SET NOT READY ERROR RETURN TO CALLING ROUTINE JUMP TO...

Страница 116: ...EMENT TRACK NUMBER SETTLE TIME RETURN TO CALLING ROUTINE CALCULATE SET NO DELTA DIRECTION f X j ISSUE STEP x PULSE 1 WAIT 10 MSEC DECREMENT DELTA DEI NO EQL T JAL YES WAIT 20 MSEC JUMP TO FIN 0 iV Fig...

Страница 117: ...i j READ DISK BYTE BYTE READ LOAD DATA INTO ACCUMULATOR RETURN TO CALLING ROUTINE Figure 6 20 READ DISK BYTE 6 23...

Страница 118: ...ORE TRACK PORTION i TRACK PART EQUAL DESIRED TRACK 7 SET TRACK EQUAL FLAG CK X YES JAL y STORE SECTOR PORTION I s NO l COUNT PAST ZEROES AND CRC f 1 A YES TURN OFF CRC NETWORK RETURN TO CALLING ROUTIN...

Страница 119: ...S OF GAP 3 TURN ON CRC NETWORK WRITE ZERO BYTE WRITE TRACK PORTION WRITE ID ADDRESS MARK WRITE ADDRESS PORTION WRITE ZERO BYTE WRITE CRC BYTES WRITE 20 BYTES OF GAP 2 TURN OFF CRC NETWORK RETURN TO FO...

Страница 120: ......

Страница 121: ...nectors serve as a mounting as well as an electrical junction seeSection 7 3 Additional protection is provided by the guide slots in the INTELLEC System cabinet The Channel and Interface Boards are ea...

Страница 122: ...ess to the Diskette Channel The base address is defined by the five most significant bits of the eight bit I O port address The three least significant bits then can be used to differentiate between e...

Страница 123: ...INT6 INT7 RELATIVE PRIORITY INTELLEC MDS SYSTEM HIGHEST ir LOWEST The following sketch shows the switch setting 3 corresponding to priority line INT2 1 If the controller is to be used in conjunction w...

Страница 124: ......

Страница 125: ...100 25 100 25 35 65 40 30 20 50 Address Setup Time to I O Command Data Setup Time to I O Command Address Hold Time from I O Command Data Hold Time from I O Command Read Data Hold Time from I O Comman...

Страница 126: ...200 DESCRIPTION Address Data Setup to Command XACK to Command Turn Off Address Hold Time Data Hold Time f Read Data Hold Time Bus Sample Delay Time REMARKS Provided by Memory Module Slave ADDRESS REA...

Страница 127: ...BCLK BREQ BPRN BUSY BPRO MASTER X U BW J r L DBPN DBYF HIGH Z MASTER Y Figure 8 2 BUS EXCHANGE TIMING 8 3...

Страница 128: ...V MB L C 1 C c c L C f L C I I H J J Q t 0 0 0 u c J 3 t f t u h 0 h i k J J 0 t t CC I i r J L Q h J h C i j J 3 c 1 c j i 5 i L 1 a j u 4 1 1 1 1 I r Mi n i o o J X T 1 u 1 T 1 1 SA i 51 oo CO _J CO...

Страница 129: ...sec TYP 10 msec 10 usec 60 msec 20 msec 250 nsec 2 usec 250 nsec 1 5 msec 166 7 msec t MAX 12 msec 300 nsec 2 8 usec DESCRIPTION Step Cycle Time Step Pulse Width Settling Time Select to Data Settling...

Страница 130: ...UJ o LU _J UJ i T 1 T i i i o I o I i 1 c E 2 u Q LU Q Q LU cc CO Q Q LU DC LU 00 CO I I UJ tu 00 u 8 6...

Страница 131: ...Q Q DC T O til cc LU 1 O cc LU o I iu cc in 06 3 O is LU D Q LU Q LU h CC T I LJU K cc to 00 0 3 O 8 7...

Страница 132: ...1 CJ Z X Z UJ Q_ X z i 1 1 Q Z i 00 QJ 3 O iZ r t t LL o LU i u CO LU QC oc 5...

Страница 133: ...ADR0 DATF DAT4 DAT3 DATD SYMBOL VOL V OH c VOL VOH VIL VIH IL IIH c VOL VOH VIL VIH IL IIH c VOL VOH VIL VIH PARAMETER DESCRIPTION Output Low Voltage Output High Voltage Capacltive Load Output Low Vo...

Страница 134: ...at V _ Input Current at V _ Capacitive Load Output Low Voltage Output High Voltage Input Low Voltage Input High Voltage Input Current at V _ Input Current at V _ Input Leakage Low Input Leakage High C...

Страница 135: ......

Страница 136: ...Low Voltage Output High Leakage Capacitive Load Input Low Voltage Input High Voltage Input Current at VIL Input Current at V _ Capacitive Load Output Low Voltage Output High Voltage Capacitive Load T...

Страница 137: ......

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