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Preface

Specification Update

Preface

This document contains information specific to the Intel® Atom™ Processor N500

series. It is a Compilation of:

•

Device sightings

•

Document sightings

•

Specification clarifications

•

Specification changes

It is intended for hardware system manufacturers and software developers.

Information types defined in the

Nomenclature

section of this document are

consolidated into this document and are no longer published in other documents. This

Affected Documents

Document Title

Document

Number/

Location

Intel® Atom™ Processor N400 series and N500 series External Design
Specifications (EDS) – Volume 1

403526

Intel® Atom™ Processor N400 series and N500 series External Design
Specifications (EDS) – Volume 2

403528

RS – Pineview Processor BIOS Writer’s Guide (BWG), Volume 1

Contact your Intel

representative for

the latest revision.

RS – Pineview Processor BIOS Writer’s Guide (BWG), Volume 2

Contact your Intel

representative for

the latest revision.

NOTES:

Contact your Intel representative to receive the latest revisions of these documents.

Содержание ATOM PROCESSOR N 500 - UPDATE REVISION 001

Страница 1: ...Document Number 324341 001 Intel Atom Processor N500 Series Specification Update September 2010 Revision 001...

Страница 2: ...ormation here is subject to change without notice Do not finalize a design with this information Intel Atom Processor N500 series may contain design defects or errors known as errata which may cause t...

Страница 3: ...Specification Update 3 Contents Preface 5 Identification Information 8 Summary Tables of Changes 10 Errata 14 Specification Changes 31 Specification Clarifications 32 Documentation Changes 33...

Страница 4: ...4 Specification Update Revision History Document Number Revision Description Date 324341 001 Initial Release September 2010...

Страница 5: ...o longer published in other documents This Affected Documents Document Title Document Number Location1 Intel Atom Processor N400 series and N500 series External Design Specifications EDS Volume 1 4035...

Страница 6: ...behavior to deviate from published specifications Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices...

Страница 7: ...hout the product s lifecycle or until a particular stepping is no longer commercially available Under these circumstances errata removed from the specification update are archived and available upon r...

Страница 8: ...cates whether the processor is an original OEM processor an OverDrive processor or a dual processor capable of being used in a dual processor system 4 The Family Code corresponds to bits 11 8 of the E...

Страница 9: ...arkings SAMPLE MARK EXAMPLE GRP1LINE1 INTEL M C YY e1 GRP2LINE1 FPO S Spec Processor Table 2 Identification Table for Intel Atom Processor N500 Series QDF S Spec MM Product Stepping Processor CPUID Co...

Страница 10: ...s stepping Blank No mark This sighting is fixed or does not exist in the listed stepping Status Plan Fix Root caused to a silicon issue and will be fixed in a future stepping Fixed Root caused to a si...

Страница 11: ...rmal Interrupts BH11 X No Fix Returning to Real Mode from SMM with EFLAGS VM Set May Result in Unpredictable System Behavior BH12 X No Fix Fault on ENTER Instruction May Result in Unexpected Value on...

Страница 12: ...a C State Exit due to a Pending External Interrupt the System May Hang BH31 X No Fix Pending x87 FPU Exceptions MF Following STI May Be Serviced Before Higher Priority Interrupts BH32 X No Fix Benign...

Страница 13: ...pecification Changes in this revision of the specification Update Number SPECIFICATION CLARIFICATIONS There are no Specification Clarifications in this revision of the specification Update Number DOCU...

Страница 14: ...nt State and higher the result could be a system hang Workaround BIOS must leave the xTPR update transactions disabled default Status For the steppings affected see the Summary Tables of Changes BH2 P...

Страница 15: ...vector does not generate an EOI therefore the spurious vector should not be used when writing the LVT Status For the steppings affected see the Summary Tables of Changes BH4 MOV To From Debug Register...

Страница 16: ...egister write This will force the store to the APIC register before any subsequent instructions are executed No commercial operating system is known to be impacted by this erratum Status For the stepp...

Страница 17: ...bit mode or if a memory address exceeds the 4GB limit while the processor is operating in 32 bit mode Implication FXSAVE FXRSTOR will incur a GP fault due to the memory limit violation as expected but...

Страница 18: ...result in unpredictable system behavior Intel has not observed this behavior in commercially available software Workaround SMM software should not change the value of EFLAGS VM in SMRAM Status For the...

Страница 19: ...e BP instructions without having an invalid stack during interrupt handling However an enabled debug breakpoint or single step trap may be taken after MOV SS POP SS if this instruction is followed by...

Страница 20: ...e Workaround None Status For the steppings affected see the Summary Tables of Changes BH16 BTS Branch Trace Store and PEBS Precise Event Based Sampling May Update Memory outside the BTS PEBS Buffer Pr...

Страница 21: ...that is executing the modified code Implication In this case the phrase unexpected or unpredictable execution behavior encompasses the generation of most of the exceptions listed in the Intel Architec...

Страница 22: ...May Fail when FREEZE_LBRS_ON_PMI is Set Problem When the FREEZE_LBRS_ON_PMI IA32_DEBUGCTL MSR 1D9H bit 11 is set future writes to IA32_DEBUGCTL MSR may not occur in certain rare corner cases Writes t...

Страница 23: ...s the CS segment register between enabling protected mode and the first far JMP Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Part 1 in the section ti...

Страница 24: ...or the address range If the two translations differ with respect to page frame permissions or memory type the processor may use a page frame permissions or memory type that corresponds to neither tran...

Страница 25: ...errupt the System May Hang Problem Under a precise set of conditions a processor waking from a C state due to a pending external interrupt may not complete the exiting process and the system may hang...

Страница 26: ...ssor may hang or may handle the benign exception Intel has not observed this erratum with any commercially available software Workaround None identified Status For the steppings affected see the Summa...

Страница 27: ...nabled IA32_APIC_BASE MSR bit 11 set to 1 or do not use MWAIT I O redirection VM entry or RSM to enter an inactive state Status For the steppings affected see the Summary Tables of Changes BH35 IRET u...

Страница 28: ...on LVDS clocks LVD_A_CLKP LVD_A_CLKN and data lines LVD_A_DAPAP 2 0 LVD_A_DATAN 2 0 may be observed Due to this erratum a glitch may be seen during power up sequence The glitch is not seen once the LV...

Страница 29: ...larly polls and clears the machine check banks as this reduces the likelihood of an overflow condition Status For the steppings affected see the Summary Tables of Changes BH41 FP Data Operand Pointer...

Страница 30: ...temperature Due to this erratum a system hang may occur or the processor may proceed to reboot Due to this erratum the system may hang or auto reboot Workaround A BIOS workaround has been identified P...

Страница 31: ...Specification Changes Specification Update 31 Specification Changes There are no specification changes in this revision of the specification update...

Страница 32: ...Specification Clarifications 32 Specification Update Specification Clarifications There are no specification clarifications in this revision of the specification update...

Страница 33: ...Documentation Changes Specification Update 33 Documentation Changes There are no document changes in this revision of the specification update...

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