Intel 82801EB, Руководство программиста

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Theory of Operation
R
14 SATA Programmer’s Reference Manual
4.1.1 Additional Register Support
Support of certain Compatible configuration options requires that the ICH5 implement an
additional hardware register that is configurable via BIOS. This register is located in the SATA
function’s PCI configuration space at offset 90h and is defined below. The usage model for this
register is described in subsequent sections.
4.1.1.1 MAP – Address Map Register – Offset 90h
This register is set by BIOS during POST. The exact value programmed into this register is based
on a BIOS setup option. Dynamic modifications of this register by BIOS as a result of POST or
some other event (e.g., docking event) is not permitted, as the underlying operating system
software may not comprehend the new device topology and may result in undefined behavior.
Bit Type Reset Description
7:3 RO 0 Reserved
2:0 RW 000
Map Value (MV): The value in the bits below indicate the address range the
SATA
port responds to, and whether or not the P-ATA and
SATA
functions are
combined
.
Bits Mapping
000
Non-combined, SATA Port 0 is primary master, SATA Port 1 is
secondary master
001
Non-combined, SATA Port 0 is secondary master, SATA Port 1
is primary master
100
Combined, SATA Port 0 is primary master, SATA Port 1 is
primary slave, P-ATA is secondary
101
Combined, SATA Port 0 is primary slave, SATA Port 1 is
primary master, P-ATA is secondary
110
Combined, P-ATA is primary, SATA Port 0 is secondary master,
SATA Port 1 is secondary slave
111
Combined, P-ATA is primary, SATA Port 0 is secondary slave,
SATA Port 1 is secondary master
Caution: Programming the MAP.MV register with values other than those specified above will result in
undefined hardware behavior.
Note: The P-ATA host controller does not implement this register.