82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide
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When performing a board layout, do not allow the CAD tool auto-router to route the differential
pairs without intervention. In most cases, the differential pairs will have to be routed manually. The
components should be laid out in the following order of priority:
1. Differential traces
2. Termination resistors
3. Bypass capacitors
4. Other components
This allows placing those components in the best locations and avoids using critical space by non-
critical components.
Note:
Measuring trace impedance for layout designs targeting 100
Ω
often results in lower actual
impedance. Designers should verify actual trace impedance and adjust the layout accordingly. If
the actual impedance is consistently low, a target of 105 to 110
Ω
should compensate for second
order effects.
It is necessary to compensate for trace-to-trace edge coupling, which can lower the differential
impedance by up to 10
Ω
, when the traces within a pair are closer than 30 mils (edge to edge).
4.1.6
Trace Length and Symmetry
As indicated earlier in
, the overall length of differential pairs should be less than four
inches measured from the Ethernet device to the magnetics.
The differential traces should be equal within 50 mils (1.25 mm) within each pair and as
symmetrical as possible. Asymmetrical and unequal length traces in the differential pairs
contribute to common mode noise. Common mode noise can degrade the receive circuit’s
performance and contribute to radiated emissions.
4.1.7
Impedance Discontinuities
Impedance discontinuities cause unwanted signal reflections. Avoid vias (signal through holes) and
other transmission line irregularities. If vias must be used, a reasonable budget is two per
differential trace. Unused pads and stub traces should also be avoided.
4.1.8
Reducing Circuit Inductance
Traces should be routed over a continuous ground plane with no interruptions. If there are vacant
areas on a ground or power plane, the signal conductors should not cross the vacant area. This
increases inductance and associated radiated noise levels. Noisy logic grounds should be separated
from analog signal grounds to reduce coupling. Noisy logic grounds can sometimes affect sensitive
DC subsystems such as analog to digital conversion, operational amplifiers, etc. All ground vias
should be connected to every ground plane; and similarly, every power via, to all power planes at
equal potential. This helps reduce circuit inductance. Another recommendation is to physically
locate grounds to minimize the loop area between a signal path and its return path. Rise and fall
times should be as slow as possible. Because signals with fast rise and fall times contain many high
frequency harmonics, which can radiate significantly. The most sensitive signal returns closest to
the chassis ground should be connected together. This will result in a smaller loop area and reduce
the likelihood of crosstalk. The effect of different configurations on the amount of crosstalk can be
studied using electronics modeling software.
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