Intel 82562EX, Руководство по конструкции

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82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide
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3.3 Designing with the 82541xx Gigabit Controllers
This section provides design guidelines specific to the 82541xx Gigabit Ethernet Controllers.
3.3.1 82541xx Ethernet Controller LAN Disable Guidelines
The 82541xx controller has a LAN disable function that is present on FLSH_SO, ball P9. This pin
can be connected to a Super IO component to allow the BIOS to disable the Ethernet port (see
Figure 4 ). If the serial Flash interface is populated, the Flash serial output pin must not interfere
with this function.
Do not attempt to use the LAN_POWER_GOOD signal for a LAN disable input on the 82541xx
device. This pin is intended to operate as a power-on reset connected to a power monitor circuit.
The input of the 82541xx FLSH_SO (pin P9) is the LAN_DISABLE# signal. It is sampled on the
rising edge of LAN_PWR_GOOD or RST#. The signal must be held valid for 80 ns after either
rising edge.
If it is sampled high, the LAN functions normally. If it is sampled low, then the following occurs:
1. The LAN is disabled.
2. The PHY is powered down.
3. Most MAC clock domains are gated.
4. Most functional blocks are held in reset.
5. PCI inputs and outputs are floated.
6. The device will not respond to PCI cycles (including configuration cycles).
7. The device is put in a low power state, which is equivalent to D3 without wakeup or
manageability.