Intel 80331, Руководство по конструкции

Страница: 12 / 148

12
Intel® 80331 I/O Processor Design Guide
Introduction
1.1.1 Terminology and Definitions
Table 1. Terminology and Definitions (Sheet 1 of 2)
Term Definition
80331 Intel
®
80331 I/O processor
Stripline
Stripline in a PCB is composed of the
conductor inserted in a dielectric with GND
planes to the top and bottom.
NOTE: An easy way to distinguish stripline
from microstrip is that you need to
strip away layers of the board to view
the trace on stripline.
Microstrip
Microstrip in a PCB is composed of the
conductor on the top layer above the dielectric
with a ground plane below
Prepreg
Material used for the lamination process of manufacturing PCBs. It consists of a layer of
epoxy material that is placed between two cores. This layer melts into epoxy when heated and
forms around adjacent traces.
Core
Material used for the lamination process of manufacturing PCBs. This material is two sided
laminate with copper on each side. The core is an internal layer that is etched.
PCB
Printed circuit board.
Example manufacturing process consists of
the following steps:
• Consists of alternating layers of core and
prepreg stacked
• The finished PCB is heated and cured.
• The via holes are drilled
• Plating covers holes and outer surfaces
• Etching removes unwanted copper
• Board is tinned, coated with solder mask
and silk screened
DDR
Double Data Rate Synchronous DRAM. Data is clocked on both rising and falling edges of the
clock.
DDR II
DDR II is backward compatible with DDR I. However, it has an increased DDR data rate to
3.2 GBytes/sec with a clock rate of 200 MHz for multiple DIMM configurations. It allows data
rate of 6.4 Gbytes/sec with a clock rate of 400 MHz for a single DIMM point to point
configuration.
DIMM Dual Inline Memory Module
Source
Synchronous
DDR
• For reads data leaves the DDR or memory controller with a data strobe. The memory
controller delays the data strobe internally to line it up with the data valid window.
• For writes the memory controller places the data strobe in the middle of the data valid
window to ensure that the correct data gets clocked into the DRAM.
SSTL_2 Series Stub Terminated Logic for 2.5 V
JEDEC Provides standards for the semiconductor industry.
DLL
Delay Lock Loop - refers to the DDR feature used to provide appropriate strobe delay to clock
in data.
Layer 1: copper
Prepreg
Layer 2: GND
Core
Layer 3: V
CC
Layer 4: copper
Prepreg
Example of a Four-Layer Stack