Intel 6300ESB ICH, Руководство по конструкции

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Intel
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855GME Chipset and Intel
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6300ESB ICH Embedded Platform Design Guide
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Using multiple devices in parallel, as allowed, to reduce package power dissipation.
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Using newer/enhanced technology and devices to lower heat generation but with equal or
better performance.
For the designer, these options are not always available or economically feasible. The most
effective method of thermal spreading and heat removal from these devices is to generate airflow
across the package and add copper fill area to the current carrying leads of the package.
The processor power delivery topology also may be modified to improve the thermal spreading
characteristic of the circuit and dramatically reduce the power dissipation requirements of the
switching MOSFET and inductor. This multi-phase topology provides an output stage of the
processor regulator, which consists of several smaller buck inductor phases that are summed
together at the processor. Each phase may be designed to handle and source a much smaller
current, which may reduce the size, quantity, and rating of the design components and may
decrease the cost and PCB area needed for the total solution. The implementation options for this
topology are discussed in the next section.
4.4 Intel
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Pentium
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M/Celeron
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M Processor
Decoupling Recommendations
Intel recommends proper design and layout of the system board bulk and high-frequency
decoupling capacitor solution to meet the transient tolerance at the processor package balls. To
meet the transient response of the processor, it is necessary to properly place bulk and
high-frequency capacitors close to the processor power and ground pins.
4.4.1 Transient Response
The inductance of the motherboard power planes slows the voltage regulator’s ability to respond
quickly to a current transient. Decoupling a power plane may be partitioned into several
independent parts. The closer the capacitor is placed to the load, the more stray inductance is
bypassed. Less capacitance is required when bypassing the inductance of leads, power planes, etc.
However, areas closer to the load have less room for capacitor placement, and trade-offs must be
made.
The processor causes very large switching transients. These sharp surges of current occur at the
transition between low power states and the normal operating states. The system designer must
provide adequate high-frequency decoupling to manage the highest frequency components of the
current transients. Larger bulk storage capacitors supply current during longer-lasting changes in
current demand.
All of this power bypassing is required because the DC-to-DC converter is relatively slow to
respond. A typical voltage converter has a reaction time on the order of 1 to 100 µs while the
processor’s current steps may be shorter than 1 ns. High-frequency decoupling is typically done
with ceramic capacitors with a very low ESR. Because of their low ESR, these capacitors may act
very quickly to supply current at the beginning of a transient event. However, because the ceramic
capacitors are small and may only store a small amount of charge, bulk capacitors are needed too.
Bulk capacitors are typically polarized with high capacitance values and unfortunately higher ESLs
and ESRs. The higher ESL and ESR of the bulk capacitor limit how quickly it may respond to a
transient event. The bulk and high-frequency capacitors working together may supply the charge
needed to stay in regulator before the regulator may react during a transient.