Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - VOLUME 1 01-2011, Техническое описание

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Datasheet, Volume 1 83
Signal Description 
6.10 Error and Thermal Protection
6.11 Power Sequencing
Table 6-12. Error and Thermal Protection
Signal Name Description
Direction/
Buffer Type
CATERR#
Catastrophic Error: This signal indicates that the system has
experienced a catastrophic error and cannot continue to operate. The
processor will set this for non-recoverable machine check errors or
other unrecoverable internal errors.
On the processor, CATERR# is used for signaling the following types of
errors:
• Legacy MCERRs – CATERR# isasserted for 16 BCLKs.
• Legacy IERRs – CATERR# remains asserted until warm or cold
reset.
O
CMOS
PECI
PECI (Platform Environment Control Interface): A serial sideband
interface to the processor, it is used primarily for thermal, power, and
error management.
I/O
Asynchronous
PROCHOT#
Processor Hot: PROCHOT# goes active when the processor
temperature monitoring sensor(s) detects that the processor has
reached its maximum safe operating temperature. This indicates that
the processor Thermal Control Circuit (TCC) has been activated, if
enabled. This signal can also be driven to the processor to activate the
TCC.
CMOS Input/
Open-Drain
Output
THERMTRIP#
Thermal Trip: The processor protects itself from catastrophic
overheating by use of an internal thermal sensor. This sensor is set
well above the normal operating temperature to ensure that there are
no false trips. The processor will stop all execution when the junction
temperature exceeds approximately 130 °C. This is signaled to the
system by the THERMTRIP# pin.
O
Asynchronous
CMOS
Table 6-13. Power Sequencing
Signal Name Description
Direction/
Buffer Type
SM_DRAMPWROK
SM_DRAMPWROK Processor Input: Connects to PCH
DRAMPWROK.
I
Asynchronous
CMOS
UNCOREPWRGOOD
The processor requires this input signal to be a clean indication that
the V
CCSA
, V
CCIO
, V
AXG
, and V
DDQ
, power supplies are stable and
within specifications. This requirement applies, regardless of the S-
state of the processor. 'Clean' implies that the signal will remain low
(capable of sinking leakage current), without glitches, from the time
that the power supplies are turned on until they come within
specification. The signal must then transition monotonically to a high
state. This is connected to the PCH PROCPWRGD signal.
I
Asynchronous
CMOS
SKTOCC#
(rPGA only)
PROC_DETECT#
(BGA)
SKTOCC# (Socket Occupied)/PROC_DETECT (Processor
Detect): Pulled down directly (0 Ohms) on the processor package to
ground. There is no connection to the processor silicon for this signal.
System board designers may use this signal to determine if the
processor is present.