TERMINAL DESCRIPTION(1/4)
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -67
Q8501: SII9135CTU (HDMI RECEIVER)
DTR-7.8
Video and Audio Pins
36-Bit Output Pixel Data Bus. Q35:0
is highly configurable using the
VDD_CONFIG register. It supports a
wide array of output formats, including
multiple RBG and YCbCr bus formats.
Using the appropriate bits in the PD
register, the output drivers can be put
into a high impedance (tri-state)
mode. A weak, internal pull-down
device brings each output to ground.
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
Q18
Q19
Q20
Q21
Q22
Q23
Q24
Q25
Q26
Q27
Q28
Q29
Q30
Q31
Q32
Q33
Q34
Q35
DE
HSYNC
VSYNC
EVNODD
16
15
14
13
10
9
8
7
3
2
1
144
141
140
139
138
135
134
133
132
129
128
127
126
123
122
121
120
117
116
115
114
111
110
109
108
19
20
21
22
8 mA
8 mA
8 mA
8 mA
12 mA
5
ODCK
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
LVTTL
Output
Data Enable
Horizontal Sync Output
Vertical Sync Output
Indicates Even or Odd Field for
Interlaced Formats
Output Data Clock
Pin Name
Pin #
Strength
Type
Dir
Description
8 mA