IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -41
BLOCK DIAGRAM
PIN CONFIGURATION
Q3661:M12L64164A-7TG (64 Mbit Syncronous DRAM)
DTR-7.8
L(U)DQM
DQ
Mode
Register
Control Logic
Column
Address
Buffer
&
Refresh
Counter
Row
Address
Buffer
&
Refresh
Counter
Bank D
Row Decode
r
Bank A
Bank B
Bank C
Sense Amplifier
Column Decoder
Data Control Circuit
Latch Circuit
Input & Out
p
ut
Buf
fer
Address
Clock
Generator
CLK
CKE
Command Deco
der
CS
RAS
CAS
WE
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
V
DD
DQ 0
V
D D Q
DQ 1
DQ 2
V
S S Q
DQ 3
DQ 4
V
D D Q
DQ 5
DQ 6
V
S S Q
DQ 7
V
DD
L D Q M
W E
C AS
R AS
C S
A
13
A
12
A
10
/AP
A
0
A
1
A
2
A
3
V
DD
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
S S Q
DQ14
DQ13
V
D D Q
DQ12
DQ11
V
S S Q
DQ10
DQ 9
V
D D Q
DQ 8
V
S S
N C
U D Q M
CL K
C K E
N C
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
S S
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge
of the system clock
Auto & self refresh
15.6 us refresh interval
