DSR-4.8
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION-4
BLOCK DIAGRAM
Q1102 : EEPROM (BR24L08FV-W)
A0
A1
A2
GND
1
2
3
4
8
7
6
5
Vcc
WP
SLC
SDA
8 k bit EEPROM ARRAY
10bit
ADDRESS
DECODER
SLAVE WORD
ADDRESS REGISTER
DATA
REGISTER
10bit
START
STOP
CONTROL LOGIC
ACK
HIGH VOLTAGE GEN.
Vcc LEVEL DETECT
PIN CONFIGURATION
A0
A1
A2
GND
Vcc
WP
SCL
SDA
BR24L08/F/FJ/FV/FVM-W
PIN NAME
PIN NAME
Vcc
GND
A0, A1
A2
SCL
SDA
WP
I/O
--
--
--
IN
IN
IN/OUT
IN
FUNCTION
Power Supply
Ground (0V)
Out of Use
Slave Address Set
Serial Clock Input
Slave and Word Address,
Serial Data Input, Serial Data Output
Write Protect Input
*
1 An open drain output requires a pull-up resistor.
*
1
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9
2
8
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2
9
8
TEL 13942296513
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
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TEL 13942296513 QQ 376315150 892498299
