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Infinite Pasternack PE11S100 Series, Руководство пользователя

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Содержание Pasternack PE11S100 Series

Страница 1: ...ack is a registered trademark of Infinite Electronics Inc User Manual PE11S100X SERIES Synthesizer Pasternack PO Box 16759 Irvine CA 92623 Phone 866 727 8376 or 949 261 1920 Fax 949 261 7451 sales pas...

Страница 2: ...ility and fitness for a particular purpose Pasternack shall not be liable for errors or incidental or consequential damages in connection with the furnishing use or performance of this document or of...

Страница 3: ...eplace the line fuse s only with fuses of the same type and rating for example normal blow time delay etc The use of other fuses or material is prohibited General Safety Information The following gene...

Страница 4: ...nvironment This instrument is designed for indoor use only Revision Control Revision Description of Changes Date 1 0 Initial Creation 08 18 2011 1 1 Pasternack Updates 05 13 2019 Acronyms PPL Phase Lo...

Страница 5: ...s 4 1 0 Applicable Products 8 2 0 General Description 8 3 0 Reference Input 8 4 0 Basic Operation 9 4 1 Initialization 9 4 2 Frequency Tuning 9 4 3 Frequency Hopping 9 4 4 CW Sweeper Mode 10 4 4 1 One...

Страница 6: ...cle Register 22 7 7 Reg 05h Reserved 22 7 8 Reg 06h Phase Freq Detector Delay Register 22 7 9 Reg 07h Charge Pump UP DN Control Register 22 7 10 Reg 08h Charge Pump Trim Offset Register 22 7 11 Reg 09...

Страница 7: ...1Bh GPO Control Register 27 7 30 Reg 1Ch Phase Detector CSP Register 28 7 31 Reg 1Dh VCO Tune Port Control Register 28 7 32 Reg 1Eh Temperature Sensor Register 28 7 33 Reg 1Fh LD VCO Ramp Busy Read On...

Страница 8: ...ency sweep functions The built in linear sweeper function performs frequency chirps with a wide variety of sweep times polarities and dwells all with an external automatic or software driven sweep tri...

Страница 9: ...m_intg in Reg 0Fh Similarly the 24 bit binary value of 1d 000001h 0000 0000 0000 0000 0000 0001 into dsm_frac in Reg 10 h In integer mode the synthesizer step size is fixed to M times phase frequency...

Страница 10: ...given by ramp_steps_number Reg 16 h and the initial ramp direction is set to be increasing or decreasing in frequency by clearing or setting ramp_ startdir_dn Reg 14 h 4 respectively Setting ramp_sing...

Страница 11: ...ency hop back to the start frequency The functions of the sweep parameters for one way sweeps are shown graphically in Figure 2 Figure 2 1 Way Sweep Control 4 4 2 Two Way Sweeps If ramp_singledir Reg...

Страница 12: ...ger is required for each step of the ramp Single step mode will function with either one way or two way ramps The operation of single step mode for a one way ramp is shown graphically in Figure 4 Figu...

Страница 13: ...of the UP and DN charge pumps consist of 5 bit charge pumps with lsb of 125 A The current gain of the pump in Amps radian is equal to the gain setting of this register divided by 2 For example if both...

Страница 14: ...l logic cells in the internal PLL are reset when the device digital power supply Vd1 is applied This is referred to as Power On Reset or just POR POR normally takes about 500 us after the Vd1 supply e...

Страница 15: ...w initiates the Write cycle WR c Host places the six address bits on the next six falling edges of SCK MSB first d Slave reads the address bits in the next six rising edges of SCK 2 7 e Host places th...

Страница 16: ...edges of SCK 8 31 MSB first f Host reads the data bits on the next 24 falling edges of SCK 8 31 g SEN is de asserted on the 32nd falling edge of SCK h The 32nd falling edge of SCK completes the cycle...

Страница 17: ...s in lock the phase of the VCO signal and the reference signal vary in time due to the phase noise of the crystal and VCO oscillators the loop bandwidth used and the presence of fractional modulation...

Страница 18: ...MHz Tref 20 nsec and hence Tjpn 178 femtoseconds A normal 3 sigma peak to peak variation in the arrival time therefore would be 3 2 Tjpn 0 756 ps If the synthesizer was in fractional mode the fraction...

Страница 19: ...widow The digital one shot window is controlled by lkd_ringosc_cfg Reg 1A h 16 15 The resulting lock detect window period is then generated by the number of ring oscillator periods defined in lkd_mon...

Страница 20: ...ase for example with an offset delay as shown in Figure 10 the mean phase of the VCO will always occur after the reference The lock detect circuit window can be made more selective with a fixed offset...

Страница 21: ...0 2 R W Reserved 479 Reserved 11 R W pfd_lkd_en 1 Enable Resetb to digital lockdetect circuit and PFD s lockdetect output gates 12 R W cp_en 1 Charge Pump Enable disable is tri stated output 13 R W ds...

Страница 22: ...tion 2 0 R W Reserved 7 Reserved 7 8 Reg 06h Phase Freq Detector Delay Register Bit Type Name Default Description 2 0 R W pfd_del_sel 2 Delay line setpoint to PFD 7 9 Reg 07h Charge Pump UP DN Control...

Страница 23: ...ge Pump EN Register Bit Type Name Default Description 0 R W cp_pull_updn_en 0 Enables CP UP Down Control Reg09 1 1 R W cp_pull_dn_upb 0 0 Forces Charge Pump Up when Reg09 0 1 1 Forces Charge Pump DN w...

Страница 24: ...t Type Name Default Description 23 0 R W dsm_seed 3A1953h unsigned seed value for modulator sets the start phase of the modulator 7 20 Reg 12h Delta Sigma Modulator Register Bit Type Name Default Desc...

Страница 25: ...onous clear for ovf undf flags 1 R W ramp_enable 0 Ramp En rstb 1 enables the CW Ramp Function 2 R W ramp_trigg 0 Write always triggers ramps if bit 2 0 if bit 2 1 Ramp will not trigger bit 2 must be...

Страница 26: ...R W Reserved 15 Reserved 7 28 Reg 1Ah Lock Detect Register Bit Type Name Default Description 9 0 R W lkd_wincnt_max 298 threshold count in the timer window to declare lock reference cycles 10 R W lkd_...

Страница 27: ...obe holds the gain of the PFD at max for anti cycle slipping gpo_sel 3 0 0100 GP03 xref_clk_in GP02 xref_sin_in GP01 sd_frac_strobe_sync internally synchronized frac strobe gpo_sel 3 0 0101 VCO Serial...

Страница 28: ...loop filter and hence opens the loop 5 R W pfds_rstb 1 CSP PFD FF rstb 1 Enables the Cycle Slip Prevention CSP feature of the PFD 7 31 Reg 1Dh VCO Tune Port Control Register Bit Type Name Default Desc...

Страница 29: ...amp_busy 0 Sweeper status flag set when ramp is busy cleared when at end of ramp or not used 7 34 Reg 20h Reserved Bit Type Name Default Description 23 0 R W Reserved 32 Reserved 7 35 Reg 21h Temperat...

Страница 30: ...urces Datasheets https www pasternack com images ProductPDF PE11S1001 pdf https www pasternack com images ProductPDF PE11S1002 pdf Website https www pasternack com nsearch aspx Category Synthesizers s...

Страница 31: ...Infinite Electronics Inc 31 Contacts Customer Support Sales Pasternack PO Box 16759 Irvine CA 92623 USA Phone 866 727 8376 949 261 1920 Fax 949 261 7451 Sales Email sales pasternack com Technical Sup...

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