Application Note
15 of 33
002-33887 Rev. *A
2022-05-25
Using the Watchdog Timer in XMC7000 family MCUs
Multi-counter WDT
Subcounter 0 and Subcounter 1: CTL, LOWER_LIMIT, UPPER_LIMIT, WARN_LIMIT, CONFIG, SERVICE, and CNT
registers
•
MCWDT_LOCK = 1
•
MCWDT_LOCK = 2
To protect the MCWDT registers, one single write access to the LOCK register is required:
•
MCWDT_LOCK = 3
3.3
MCWDT interrupts
MCWDT supports different types of interrupts.
3.3.1
Pre-warning interrupt
Subcounter 0 and Subcounter 1 behave very similarly to the pre-warning interrupt of the Basic WDT. See
Warning interrupt. The only difference is that the WARN_LIMIT is a 16-bit value that can generate an interrupt
timing per the following equation:
𝑡
𝑊𝐴𝑅𝑁_𝐼𝑅𝑄
=
𝑊𝐴𝑅𝑁_𝐿𝐼𝑀𝐼𝑇
𝑓
𝐿𝐹𝐶𝐿𝐾
The interrupt can be used as a pre-warning event that indicates that the MCWDT counter must be serviced
before a FAULT event is issued.
The interrupt is triggered to the related CPU when the WARN_ACTION[8] bit is set to ‘1’ in the CONFIG register.
The MCWDT can be serviced automatically by the AUTO_SERVICE[12] bit in the CONFIG register. This allows the
creation of a periodic interrupt if this counter is not needed as a watchdog.
3.3.2
MCWDT Subcounter 2 interrupt
Subcounter 2 interrupt behaves in a different way. A coarse-grained timing should be generated when a
dedicated pre-defined counter bit is toggled. The interrupt timing is calculated with the following equation:
𝑡
𝐼𝑅𝑄
= 2
𝑛
1
𝑓
𝐿𝐹𝐶𝐿𝐾
Example:
LFCLK = ILO0 = 32.768 kHz
Toggle-Bit = Bit 12
𝑡
𝐼𝑅𝑄
= 2
12
1
32768
= 125 𝑚𝑠
The toggle-bit is configured by BITS[20:16] in the CTR2_CONFIG register. The interrupt is triggered to the
related CPU when the ACTION[0] bit is set to ‘1’ in the CTR2_CONFIG register.
3.4
Timeout mode
This mode is related to Subcounter 0 and Subcounter 1 only, and is similar to that of the basic WDT. See
Timeout mode. The difference is that the UPPER_LIMIT is a 16-bit value; when the subcounter matches with
the UPPER_LIMIT value, a FAULT is generated to be handled in the FAULT structures.
