Application Note
6 of 19
001-87564 Rev.*D
2021-06-01
A Design Guide to SPI F-
RAM™ Processor Companion
- FM33256B
Processor Companion Features
r e s t r i c t e d
forces a reset condition when the timer restart occurs too late (the programmed end time (register 0Ch) for the
Watchdog Timer window is exceeded). The timer may be restarted at any time within the timeout window by
writing 1010b to the Watchdog Restart register (register 0Ah).
When a reset condition occurs, the device will set one of the three flags to indicate the source of the reset in the
register 09h: EWDF, LWDF, and POR. These bits are battery-backed during power-down. After power is restored,
the system host can read these bits to determine the cause of the reset. The host must clear these bits after
reading them.
A manual hardware reset may be provided in the system by simply connecting a momentary contact switch to
the
RST
̅̅̅̅̅
pin. The
RST
̅̅̅̅̅
pin detects an external LOW input condition and responds by driving the
RST
̅̅̅̅̅
signal LOW
for 100 ms (maximum). This effectively filters and debounces a reset switch. Note that in all reset cases, the
chip internally drives a Lockout signal that serves to block any SPI traffic and abort any pending write accesses
to the F-RAM.
4.2
Early Power-Fail Warning
The F-RAM integrated Processor Companion features a general-purpose comparator that can be used to
generate an early power-fail interrupt (PFI). This warning signal can drive a microcontroller interrupt input and
must occur before V
DD
drops too low to save all critical data to the nonvolatile RAM.
The processor companion’s
early power-fail interrupt can also be used as a warning to the system to stop conducting critical activity during
a brownout condition. For more information, refer to the application note
AN400 - Generating a Power-Fail
Interrupt using the F-RAM Processor Companion
4.3
Event Counter
The FM33256B device integrates a 16-bit event counter for tamper detection or other event-logging purposes.
The counter has an input pin (CNT) that is edge-triggered and polarity that is user-defined. The event, or edge,
must be CMOS-logic level. The counter control register is nonvolatile and counter values are either battery-
backed or nonvolatile based on the Nonvolatile/Volatile Counter (NVC, in register 0Dh, bit 7) user selection.
The event counter can be operated in two modes.
•
Continuous mode (POLL = 0, register 0Dh, bit 1)
•
Polled mode (POLL = 1, register 0Dh, bit 1)
In continuous mode, the CNT pin is continuously monitored for any event and the event counter is incremented
when an event is detected. The polarity of the event can be either a rising edge (Counter Polarity bit, CP = 1,
register 0Dh, bit 0) or a falling edge (CP = 0, register 0Dh, bit 0). The events which occur as fast as 1 KHz can be
detected in this mode. Depending on the application, you can set the event counter to work on either V
DD
or
V
BAK
. If events occur when power is down, event counter should work on V
BAK
(NVC = 0 in register 0Dh, bit 7).
Otherwise, it can be configured to work on V
DD
(NVC = 1 in register 0Dh, bit 7) which will result in longer battery
life.
Note:
In continuous mode, a pull-up resistor on CNT pin should be connected appropriately to either the
backup supply V
BAK
or V
DD
.
Continuous mode is not suitable for detecting tamper events which are generally one-time or low-frequency
events and can occur when power is down. In such cases, polled mode can be used. Polled mode works only
with battery-backed (NVC = 0, register 0Dh, bit 7) and rising- edge detection (CP = 1, register 0Dh, bit 0)
configuration. In polled mode, the CNT pin is polled once every 125 ms resulting in a reduced power
consumption and longer battery life. The value in the event counter may not represent the actual number of
tamper events, but a positive value indicates a tamper.
